Information processing device and memory anomaly monitoring method
AssigneeFujitsu Limited
InventorShin Endou
Life of this patent
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Abstract
The present invention provides an information processing device having a CPU which executes an OS and firmware, and a plurality of memory controllers which are connected to the CPU, control writing to and reading from a plurality of memory units, and perform error monitoring, wherein the plurality of memory units each connected to the plurality of memory controllers, the memory controllers sequentially read memory areas of the plurality of memory units connected to the memory controllers, and perform error area monitoring, and the firmware converts addresses recognized by the memory controllers corresponding to the error areas into logical addresses recognized by the OS, and supplies the logical addresses to the OS.
Claims10
An information processing device, comprising:
- a processor which executes an OS and firmware;
- and
- a plurality of memory units where each of the memory units is coupled to a memory controller and has a memory area capable of having different memory size due to memory expansion, wherein
- the memory controller which is coupled to the processor, controls writing to and reading from each of the memory areas of the plurality of memory units, and performs error monitoring for monitoring error memory area in the each of memory areas,
- the memory controller detects the physical address of the error memory area,
- the firmware performs address conversion to convert the physical address of the error memory area into a logical address recognized by the OS on the basis of the memory size with expanded memory and supplies the logical address to the OS, and
- the OS executes error processing on the basis of the logical address received from the firmware.
A memory anomaly monitoring method in an information processing device having a processor which executes an OS and firmware, a plurality of memory units where each of the memory units is coupled to a memory controller and has a memory area capable of having different memory size due to memory expansion, the memory controller which is coupled to the processor, controls writing to and reading from each of the memory areas of the plurality of memory units, and performs error monitoring for monitoring error memory area in the each of memory areas, the method comprising:
- detecting the physical address of the error memory area, by the memory controller,
- performing address conversion to convert the physical address of the error memory area into a logical address recognized by the OS on the basis of the memory size with expanded memory, and supplying the logical address to the OS, by the firmware, and
- executing error processing on the basis of the logical address received from the firmware, by the OS.
Dependencies are inferred from the claim text.