Memory device data latency circuits and methods

A memory device, comprising:

• at least one memory cell array;
• a read first-in-first-out circuit (FIFO) configured to output read data from the at least one memory cell array according to a periodic clock signal;
• a write FIFO configured to input write data in response to a FIFO control signal that is synchronous with the periodic clock signal;
• and
• a control circuit configured to activate the FIFO control signal with a predetermined latency with respect to at least a first input command corresponding to the write data.

A method, comprising:

• establishing a latency of an integrated circuit (IC) device write data path by operation of a write first-in-first-out circuit (FIFO);
• transferring write data between at least one memory cell array and connections of the IC device via at least the write FIFO;
• establishing a latency of an IC device write address path by operation of a shift-register circuit;
• and
• transferring write addresses in parallel with the write data via the shift-register circuit;
• transferring read data through a self-timed circuit from the memory cell array to a read FIFO independently of a periodic clock signal;
• and
• transferring read data through the read FIFO in a synchronism with the periodic clock signal.