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US 8,527,796 B2Granted
Providing adaptive frequency control for a processor using utilization information
AssigneeIntel Corporation
InventorJames B. Werner
Life of this patent
Estimating the term…
Abstract
In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the core clock signal based on the determined operating frequency. Other embodiments are described and claimed.
Claims20
A processor comprising:
- at least first and second thread units each including a first counter to provide a first count value and a second counter to provide a second count value, wherein the first counter and the second counter are to run at a first core clock frequency, the first count value corresponding to a number of total clock cycles and the second count value corresponding to a number of active clock cycles;
- and
- a controller coupled to the at least first and second thread units to receive the first and second count values and to calculate a utilization value for each of the first and second thread units based thereon, and to determine a ratio used to set a core clock frequency based at least in part on the utilization values, a target utilization value, and a current ratio.
A method comprising:
- receiving utilization data from at least a first thread unit and a second thread unit of a first processor core;
- determining an operating frequency for a core clock signal based on the utilization data, a target utilization value corresponding to a threshold utilization value, and an operating mode of a processor including the first processor core;
- and
- generating the core clock signal based on the determined operating frequency.
1 more element
A system comprising:
- a processor including a plurality of cores each having a plurality of thread units each to store an architectural state for a corresponding thread and including a first counter and a second counter, the first and second counters to run at a first core clock frequency, the first counter to output a first count value and the second counter to output a second count value, a logic coupled to the plurality of cores to receive the first and second count values and to calculate a utilization value for each of the plurality of thread units of the plurality of cores based thereon, and to determine a ratio used to set a core clock frequency based on the utilization values, a target utilization value for the processor, and a current ratio of the processor;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
Dependencies are inferred from the claim text.