US 8,527,741 B2Granted

System for selectively synchronizing high-assurance software tasks on multiple processors at a software routine level

AssigneeViaSat, Inc.

InventorsAlbert J. Bourdon, Gary G. Christensen, Michael J. Godfrey

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Abstract

A task matching circuit for synchronizing software on a plurality of processors is disclosed. The task matching circuit includes first and second inputs, an analysis sub-circuit, and an output. The first input is from a first processor configured to receive a first software routine identifier. The second input is from a second processor configured to receive a second software routine identifier. The analysis sub-circuit determines if the first software routine identifier corresponds with the second software routine identifier. The output is coupled to at least one of the first or second processors and indicates when the first and second software routine identifiers do not correspond. One of the first and second processors is delayed until the first and second software routine identifiers correspond.

Claims19

Dependent claims

A task matching circuit for synchronizing software on a plurality of processors, the task matching circuit comprising:

a first input from a first processor configured to receive a first software routine identifier, wherein one value of the first software routine identifier uniquely identifies, based on the one value of the first software routine identifier, a first routine to be executed by the first processor, the first routine being one of a plurality of routines and comprising a predetermined plurality of software instructions;
a second input from a second processor configured to receive a plurality of second software routine identifiers from a queue of second software routine identifiers, wherein:
each of the plurality of second software routine identifiers uniquely identifies a corresponding one of a plurality of second routines to be executed by the second processor, and
each of the second routines is one of the plurality of routines and comprises a predetermined plurality of software instructions;
an analysis sub-circuit, at least partially embodied in hardware, configured to compare the first software routine identifier with each of the plurality of second software routine identifiers and determine if the first software routine identifier and a presently compared one of the second software routine identifiers correspond to a same routine;
and
an output coupled to at least one of the first or second processors, wherein:
the output indicates when the first software routine identifier and one of the plurality of second software routine identifiers do not correspond to the same routine, and
the analysis sub-circuit is configured to delay the first processor, and select each of the plurality of second software routine identifiers in the queue of second software routine identifiers, without the second processor executing a second routine corresponding to a presently selected second software routine identifier, until the first software routine identifier and the presently selected second software routine identifier correspond to the same routine.

6 more elements

A high-assurance circuit for coordinating performance on a plurality of sub-circuits, the high-assurance circuit comprising:

a first input from a first sub-circuit configured to receive a first operation identifier, wherein one value of the first operation identifier uniquely identifies, based on the one value of the first operation identifier, a first software operation comprising a predetermined plurality of software instructions to be executed by the first sub-circuit, the first software operation being one of a plurality of software operations;
a second input from a second sub-circuit configured to receive a plurality of second operation identifiers from a queue of second operation identifiers, wherein:
each of the plurality of second operation identifiers uniquely identifies a corresponding one of a plurality of second software operations to be executed by the second sub-circuit, and
each of the second software operations comprises a predetermined plurality of software instructions;
an analysis sub-circuit, at least partially embodied in hardware, configured to compare the first operation identifier with each of the plurality of second operation identifiers and determine if the first operation identifier corresponds with a presently compared one of the second operation identifiers;
and
an output coupled to at least one of the first or second sub-circuits, wherein:
the output indicates when the first operation identifier and one of the plurality of second operation identifiers do not correspond to functionally overlapping software operations, and
the analysis sub-circuit is configured to delay the first sub-circuit, and select each of the plurality of second operation identifiers in the queue of second operation identifiers, without the second sub-circuit executing a second software operation corresponding to a presently selected second operation identifier, until the first operation identifier and the presently selected second operation identifier correspond to functionally overlapping software operations.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/428,508Filed 3 Jul 2006 · us provisional application
Priority: 5 Jul 2005
Published: US 2007/0113224 A117 May 2007
Granted: 3 Sep 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 9/52
Multiprogramming arrangements: program synchronisation; Mutual exclusion, e.g. by means of semaphores
G06F 9/522
Program synchronisation; Mutual exclusion, e.g. by means of semaphores: barrier synchronisation
G06F
Computing and data processing