Apparatus and method for a synchronous multi-port memory
AssigneeCypress Semiconductor Corporation
InventorRishi Yadav
Life of this patent
Estimating the term…
Abstract
A multi-port memory, comprising: a plurality of ports, each port including port input logic that generates a write enable value from received control signals, and a delay stage coupled to store the write enable value from the input stage, and configured to force the write enable value to a disable state in response to an asserted busy signal of the port; and an arbitration circuit coupled to the ports that arbitrates contending accesses to the ports by de-asserting a busy signal to one port, and asserting a busy signal for all other ports.
Claims18
A multi-port memory, comprising:
- a plurality of ports, each port including
- port input logic that generates a write enable value and a read enable value from received control signals, and
- a delay stage coupled to store the write enable value from the port input logic, and configured to force the stored write enable value to a disable state in response to an asserted busy signal of the port;
- and
- an arbitration circuit coupled to the ports that arbitrates contending accesses to the ports by de-asserting a busy signal to one port, and asserting a busy signal for all other ports;
- control logic that logically combines the read and write enable values of the port to generate an applied write enable value for the port;
- and
- a memory array having write enable inputs coupled to receive the applied write enable values of each port.
A multi-port memory, comprising:
- a plurality of ports, each port including
- a delay stage that delays address values and write enable values received from an input stage, and
- an address multiplexer (MUX) having a first input coupled to receive an address value input to the delay stage, a second input coupled to receive a delayed address value output from the delay stage, a control input coupled to receive a read enable value, and an output coupled to output address values to a memory array, and a read enable latch having an input coupled to receive the read enable value from an input stage and an output coupled to the control input of the address MUX;
- wherein
- each input stage further includes control logic that logically combines read enable signals with write enable signals to generate an applied write enable signal for input to the memory array.
A method, comprising:
- storing address, read enable data, and write enable data for competing accesses on different ports of a memory device;
- arbitrating between the competing accesses to determine one prevailing access, with the remaining accesses being nonprevailing accesses;
- for all nonprevailing accesses that are write accesses, setting the stored write enable data to an inactive value;
- logically combining at least the read and write enable data of the same port to generate an applied write enable value;
- and
- controlling write operations to a memory array according to the applied write enable values of the different ports.
Dependencies are inferred from the claim text.