Concurrent access to a memory pool shared between a block access device and a graph access device

An apparatus, comprising:

• a memory pool shared between a graph access device and a block access device;
• means for monitoring one or more memory block access operations performed by the block access device while accessing the memory pool;
• means for modifying a graph data structure based on the memory block access operations, the graph data structure including a plurality of pointers mapping the memory pool to a hierarchical file system;
• means for the graph access device accessing the memory pool concurrently with the block access device, according to the graph data structure;
• means for the block access device to attemptwriting to a first memory block in the memory pool;
• means for determining whether the graph access device is presently accessing the first memory block, wherein if the graph access device is presently accessing the first memory block, the block access device writes to a second memory block instead of the first memory block;
• and
• means for resolving the graph data structure to indicate at least one memory location of the write performed by the block access device.

A peripheral device, comprising:

• a memory shared between a graph access device and a block access device;
• a first communication interface configured to communicate with the block access device;
• a second communication interface configured to communicate with the graph access device;
• a processor, operatively coupled to the memory, and the first and second communication interfaces, configured to:
• monitor one or more memory block access operations performed by the block access device while accessing the memory;
• modify a graph data structure based on the memory block access operations, the graph data structure including a plurality of pointers mapping the memory to a hierarchical file system;
• and
• permit the graph access device to concurrently access the memory, according to the graph data structure, while the block access device is also accessing the memory;
• determine whether the block access device attempting to write to a first memory block in the memory pool;
• determine whether the graph access device is presently accessing the first memory block, wherein if the graph access device is presently accessing the first memory block, the block access device writes to a second memory block instead of the first memory block;
• and
• resolve the graph data structure to indicate at least one memory location of the write performed by the block access device.

A non-transitory computer-readable medium embodying a set of instructions executable by one or more processors, comprising:

• code for monitoring one or more memory block access operations performed by the block access device while accessing the memory pool;
• code for modifying a graph data structure based on the memory block access operations, the graph data structure including a plurality of pointers mapping the memory pool to a hierarchical file system;
• code for the graph access device accessing the memory pool concurrently with the block access device, according to the graph data structure;
• code for determining whether the block access device is attempting to write to a first memory block in the memory pool;
• code for determining whether the graph access device is presently accessing the first memory block;
• wherein if the graph access device is presently accessing the first memory block, the block access device writing to a second memory block instead of the first memory block;
• and
• code for resolving the graph data structure to indicate at least one memory location of the write performed by the block access device.