Detecting address conflicts in a cache memory system
AssigneeInternational Business Machines Corporation
InventorAndrew K. Martin
Life of this patent
Estimating the term…
Abstract
A cache memory providing improved address conflict detection by reference to a set associative array includes a data array that stores memory blocks, a directory of contents of the data array, and a cache controller that controls access to the data array. The cache controller includes an address conflict detection system having a set-associative array configured to store at least tags of memory addresses of in-flight memory access transactions. The address conflict detection system accesses the set-associative array to detect if a target address of an incoming memory access transaction conflicts with that of an in-flight memory access transaction and determines whether to allow the incoming transaction memory access transaction to proceed based upon the detection.
Claims12
A cache memory, comprising:
- a data array that stores memory blocks;
- a directory of contents of the data array;
- and
- a cache controller that controls access to the data array, the cache controller including an address conflict detection system including a set-associative array configured to store at least tags of memory addresses of in-flight memory access transactions, wherein the set-associative array includes a plurality of sets each including multiple ways that store at least tags of memory addresses of in-flight memory access transactions;
- wherein the address conflict detection system accesses the set-associative array to detect if a target address of an incoming memory access transaction conflicts with that of an in-flight memory access transaction and determines whether to allow the incoming memory access transaction to proceed based upon the detection;
- wherein the address conflict detection system allocates a way to the incoming memory access transaction within a set of the set-associative array determined by an index field of the target address if an address conflict is not detected.
A data processing system, comprising:
- a processor core;
- and
- cache memory coupled to the processor core, the cache memory including
- a data array that stores memory blocks;
- a directory of contents of the data array;
- and
- a cache controller that controls access to the data array, the cache controller including an address conflict detection system including a set-associative array configured to store at least tags of memory addresses of in-flight memory access transactions, wherein the set-associative array includes a plurality of sets each including multiple ways that store at least tags of memory addresses of in-flight memory access transactions;
- wherein the address conflict detection system accesses the set-associative array to detect if a target address of an incoming memory access transaction conflicts with that of an in-flight memory access transaction and determines whether to allow the incoming transaction memory access transaction to proceed based upon the detection;
- wherein the address conflict detection system allocates a way to the incoming memory access transaction within a set of the set-associative array determined by an index field of the target address if an address conflict is not detected.
A method of data processing system, comprising:
- receiving at least a tag of a target address of an incoming memory access transaction of a cache memory;
- accessing a set-associative array to detect whether the target address of the incoming memory access transaction conflicts with that of an in-flight memory access transaction;
- in response to the detection, permitting the incoming memory access transaction to proceed if no address conflict is detected and preventing the incoming memory access transaction from proceeding if an address conflict is detected;
- and
- allocating a way to the incoming memory access transaction within a set of the set-associative array determined by an index field of the target address if an address conflict is not detected.
Dependencies are inferred from the claim text.