Closed loop dynamic interconnect bus allocation method and architecture for a multi layer SoC

A non transitory computer readable storage medium for allocating on chip bus transactions between multiple masters and multiple slaves via multiple buses in an SoC, having instructions that, when executed by a computing device causes the computing device to perform a method comprising:

• receiving the on chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves by an interconnect module via the multiple buses;
• receiving inner characteristic information of the on chip bus transactions based on the multiple masters and the one or more of the multiple slaves via an inner characteristic bus by the interconnect module, wherein the inner characteristic bus is separate from the multiple buses in the SoC, and the inner characteristic bus does not convey any of the on chip bus transactions from any of the multiple masters;
• and
• allocating the received on chip bus transactions from the multiple masters to associate one or more of the multiple slaves based on the received inner characteristic information of the on chip bus transactions by the interconnect module.

An SoC, comprising:

• multiple masters;
• multiple slaves;
• multiple buses;
• an interconnect module coupled to the multiple masters and the multiple slaves via the multiple buses;
• and
• an inner characteristic bus coupled to the multiple masters, the multiple slaves and the interconnect module, wherein the interconnect module receives on chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves via the multiple buses, wherein the inner characteristic bus is separate from the multiple buses in the SoC, and the inner characteristic bus does not convey any of the on chip bus transactions from any of the multiple masters, wherein the interconnect module receives inner characteristic information of the on chip bus transactions based on the multiple masters and the one or more of the multiple slaves via the inner characteristic bus, and wherein the interconnect module allocates the received on chip bus transactions from the multiple masters to associate one or more of the multiple slaves based on the received inner characteristic information of the on chip bus transactions.