Reducing latency in serializer-deserializer links
AssigneeMoSys, Inc.
InventorsMichael J. Morrison, Jay B. Patel, Philip A. Ferolito, Michael J. Miller
Life of this patent
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Abstract
A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.
Claims20
A method for reducing data latency during deserialization of one or more lanes of serial data, the method comprising:
- (a) providing a double buffer having an upper buffer half and a lower buffer half,
- (b) sequentially writing pairs of deserialized bits of the serial data to the upper buffer half at a first clock speed of a first clock signal,
- (c) when the upper buffer half is full, reading all data from the upper buffer half in parallel into a physical coding sublayer at a second clock speed of a system clock signal, wherein the second clock speed is less than and dependent on the first clock speed,
- (d) sequentially writing pairs of deserialized bits of the serial data to the lower buffer half at the first clock speed,
- (e) when the lower buffer half is full, reading all data from the lower buffer half in parallel into the physical coding sublayer at the second clock speed, and
- (f) aligning the data from the upper buffer half and the lower buffer half in the physical coding sublayer.
A data interface for reducing data latency during deserialization of one or more lanes of serial data, the data interface comprising:
- a first clock for generating a first clock signal having a first clock speed,
- a second clock for generating a second clock signal having a second clock speed that is less than and dependent on the first clock speed, and
- a double buffer having:
- an upper buffer half into which pairs of deserialized bits of the serial data are sequentially written at the first clock speed, and from which all stored data is read in parallel into a physical coding sublayer at the second clock speed when the upper buffer half is full, and
- a lower buffer half into which pairs of deserialized bits of the serial data are sequentially written at the first clock speed, and from which all stored data is read in parallel into the physical coding sublayer at the second clock speed when the lower buffer half is full,
- wherein the data from the upper buffer half and the lower buffer half are aligned in the physical coding sublayer.
A data interface for reducing data latency during deserialization of one or more lanes of serial data, the data interface comprising:
- means for deserializing bits of the serial data, and providing the deserialized bits at a first clock speed in response to a first clock signal;
- a double buffer having an upper buffer half and a lower buffer half;
- means for sequentially writing a first set of the deserialized bits to the upper buffer half at the first clock speed;
- means for sequentially writing a second set of the deserialized bits to lower buffer half at the first clock speed;
- means for reading the first set of the deserialized bits from the upper buffer half in parallel into a physical coding sublayer at a second clock speed of a system clock signal when the upper buffer half is full, wherein the second clock speed is less than and dependent on the first clock speed;
- means for reading the second set of the deserialized bits from the lower buffer half in parallel into the physical coding sublayer at the second clock speed when the lower buffer half is full;
- and
- means for aligning the first and second sets of deserialized bits in the physical coding sublayer.
Dependencies are inferred from the claim text.