Distributed micro instructions set processor architecture for high-efficiency signal processing

A wireless communication base station comprising:

• a plurality of hardware planes, at least one of the hardware planes comprising a plurality of kernels, each kernel including an application specific instruction set processor (ASISP) configured to support at least one process hosted by the wireless communication base station and to track process state information associated with the at least one process;
• a controller configured to control a processing schedule for the plurality of hardware planes of the wireless communication base station;
• and
• a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process.

A wireless communication method comprising:

• processing, by a plurality of application specific instruction set processors (ASISPs), one or more processes of a base station;
• tracking, by the plurality of ASISPs, process state information associated with each of the processes;
• storing, in a memory, the tracked process state information;
• and
• retrieving, from the memory, process state information for a second process when an ASISP of the plurality of ASISPs is reallocated from a first process to the second process.