Shift register

A shift register comprising a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other, wherein each of the stages comprises:

• a node controller for controlling a charging duration of a set node;
• and
• an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node,
• wherein the node controller maintains the charging duration for a time corresponding to a low duration of any one of a plurality of clock pulses having phase differences therebetween, and
• the output unit outputs the corresponding scan pulse of a high state for the charging duration by selectively outputting a first charging voltage for the charging duration, the first charging voltage being a direct current (DC) voltage,
• wherein the plurality of clock pulses are sequentially output in such a manner that low durations thereof partially overlap with each other,
• wherein the output unit comprises a pull-up switching device controlled by a voltage at the set node and connected between a first charging voltage line transferring the first charging voltage and the output terminal,
• wherein the output unit further comprises a pull-down switching device controlled by any one of the clock pulses and connected between the output terminal and a first discharging voltage line transferring a first discharging voltage, and
• wherein the node controller of an nth one of the stages (where n is a natural number) comprises:
• a first switching device controlled by any one of the clock pulses and connected between the output terminal of an (n−p)th one of the stages (where p is a natural number less than n) and a forward preset node;
• a second switching device controlled by any one of the clock pulses and connected between a common preset node and a second discharging voltage line transferring a second discharging voltage;
• a third switching device controlled by any one of the clock pulses and connected between the set node and the second discharging voltage line;
• a fourth switching device controlled by a voltage at the forward preset node and connected between a forward voltage line transferring a forward voltage and the common preset node;
• a fifth switching device controlled by a voltage at the common preset node and connected between a second charging voltage line transferring a second charging voltage and the set node;
• a sixth switching device controlled by any one of the clock pulses and connected between a reverse preset node and the output terminal of an (n+q)th stage (where q is a natural number);
• and
• a seventh switching device controlled by a voltage at the reverse preset node and connected between the common preset node and a reverse voltage line transferring a reverse voltage,
• wherein the first switching device, the second switching device, the third switching device, the sixth switching device and the pull-down switching device are all supplied with the same clock pulse,
• wherein the clock pulse supplied to the first switching device, the second switching device, the third switching device, the sixth switching device and the pull-down switching device has a low duration coinciding with a high duration of a scan pulse output from the nth stage, and
• wherein the clock pulse supplied to the first switching device, the second switching device, the third switching device, the sixth switching device and the pull-down switching device has a high duration partially overlapping with a high duration of a scan pulse from the (n−p)th stage or a high duration of a scan pulse from the (n+q)th stage.