Communication systems and clock generation circuits thereof with reference source switching
AssigneeMediatek Inc.
InventorsKuan-Hua Chao, Shiue-Shin Liu, Tse-Hsiang Hsu
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Abstract
A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL generates the output clock signal according to a second clock signal.
Claims11
A device communicating with a host, comprising:
- a receiver for receiving and recovering host data (DH) from the host to generate a host clock signal (clkr);
- a clock generator for generating a local clock signal;
- a phase locked loop (PLL) for generating an output clock signal (clkout);
- and
- a transmitter for transmitting device data according to the output clock signal,
- wherein before the receiver receives the host data, the PLL generates the output clock signal according to the local clock signal,
- wherein after the receiver receives the host data, the PLL generates the output clock signal according to the host clock signal when a frequency of the output clock signal generated according to the local clock signal is not within a range required for specification of the transmitter, and
- wherein the host clock signal (clkr) is different from the local clock signal, and the host clock signal is within the range required for the specification of the transmitter.
A communication system, comprising:
- a host comprising a host transmitter and a host receiver, wherein the host transmitter transmits host data;
- and
- a device for communicating with the host and receiving the host data, wherein the device comprises:
- a device receiver for receiving and recovering the host data to generate a host clock signal;
- a clock generator for generating a local clock signal;
- a phase locked loop (PLL) for generating an output clock signal;
- and
- a device transmitter for transmitting device data to the host transmitter according to the output clock signal,
- wherein before the device receiver receives the host data from the host transmitter, the PLL generates the output clock signal according to the local clock signal,
- wherein after the device receiver receives the host data from the host transmitter, the PLL generates the output clock signal according to the host clock signal when a frequency of the output clock signal generated according to the local clock signal is not within a range required for specification of the transmitter, and
- wherein the host clock signal is different from the local clock signal, and the host clock signal is within the range required for the specification of the transmitter.
Dependencies are inferred from the claim text.