US 8,526,267 B2Granted

Electronic device

AssigneeRenesas Electronics Corporation

InventorsMotoo Suwa, Toshikazu Matsuda

Life of this patent

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Abstract

To suppress a timing window from being narrowed undesirably by the harmonic component of a signal output from a semiconductor component without imposing a burden on the semiconductor component that controls access. A capacitor element is arranged in series with a specific transmission path branching from a predetermined node of a signal transmission path and reaching to a ground plane, the signal transmission path supplying an enable control signal that indicates the validity of a clock signal and a command and address signal output from a semiconductor component that controls access on a substrate to another semiconductor component to be accessed on the substrate. The capacitor element functions as a short-circuit path to the ground plane for the harmonic component of the enable control signal and makes smaller the through rate and makes larger the timing window of the enable control signal compared to those when the capacitor element is not provided.

Claims16

Dependent claims

An electronic device comprising:

a substrate having a plurality of first terminals formed in a first semiconductor component mounting region, a plurality of second terminals formed in a second semiconductor component mounting region, and transmission paths coupling the first terminals and the second terminals, respectively;
a first semiconductor component mounted in the first semiconductor component mounting region;
and
a second semiconductor component mounted in the second semiconductor component mounting region,
wherein the second semiconductor component has plurality of memory devices operated in synchronization with a clock signal,
wherein the first semiconductor component has a memory controller controlling the second semiconductor component,
wherein the transmission paths include a clock transmission path to supply the clock signal from the first semiconductor component to the second semiconductor component, a command/address transmission path to supply a command and address signal from the first semiconductor component to the second semiconductor component, a data system transmission path to transmit data between the first semiconductor component and the second semiconductor component, and a first control system transmission path to transmit a first control system signal to indicate the validity of the clock signal and the command and address signal from the first semiconductor component to the second semiconductor component,
wherein the substrate further has a ground plane, a first specific transmission path branching from the middle of the first control system transmission path and reaching the ground plane, and a first capacitor element arranged in series with the first specific transmission path, and
wherein the first capacitor element has a capacitance value greater than a parasitic capacitance of a path from the proximal end in the direction of signal transmission of the first control system transmission path to the branching point to the first specific transmission path.

6 more elements

An electronic device in which a first semiconductor component and a second semiconductor component controlled by the first semiconductor component are mounted on a substrate,

wherein the second semiconductor component has a plurality of memory devices operated in synchronization with a clock signal,
wherein the substrate has a plurality of signal paths to couple the second semiconductor component to the first semiconductor component,
wherein the signal paths include a clock transmission path to supply the clock signal from the first semiconductor component to the second semiconductor component, a command/address transmission path to supply a command and address signal from the first semiconductor component to the second semiconductor component, a data system transmission path to transmit data between the first semiconductor component and the second semiconductor component, and a first control system transmission path to transmit a first control system signal to indicate the validity of the clock signal and the command and address signal from the first semiconductor component to the second semiconductor component,
wherein the substrate further has a ground plane, specific transmission path branching from the middle of the first control system transmission path and reaching the ground plane, and a capacitor element arranged in series with the specific transmission path, and
wherein the capacitor element makes smaller the through rate and makes larger the timing window of the first control system signal compared to those when the capacitor element is not provided.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/170,663Filed 28 Jun 2011
Priority: JP 2010-14614228 Jun 2010
Published: US 2011/0317475 A129 Dec 2011
Granted: 3 Sep 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 5/04
Disposition of storage elements, e.g. in the form of a matrix array: supports for storage elements , e.g. memory modules; Mounting or fixing of…
H05K 1/0231
Using auxiliary mounted passive components or auxiliary substances: capacitors or dielectric substances
H05K 2201/10159
Types of components: memory
G11C
Static stores