Three state word line driver for a DRAM memory device

A memory system comprising:

• a plurality of memory banks, each comprising an array of memory cells arranged in rows and columns, a plurality of word lines, wherein each of the word lines is connected to gates of access transistors in a corresponding row of the memory cells, whereby a voltage applied to the word line is simultaneously applied to the gates of the access transistors in the corresponding row of memory cells, and a plurality of word line drivers coupled to the word lines;
• and
• means for applying a first supply voltage to word line drivers in memory banks that are being accessed, and applying a second supply voltage to word line drivers in memory banks that are not being accessed, wherein the first and second supply voltages, when applied by the word line drivers to the word lines in the memory banks that are being accessed and the memory banks that are not being accessed, turn off access transistors of the memory cells, wherein the first supply voltage turns off the access transistors harder than the second supply voltage.

A method of operating a memory bank comprising:

• applying a first supply voltage to non-selected word lines of the memory bank while the memory bank is being accessed, wherein each of the non-selected word lines applies the first supply voltage to gates of access transistors in a corresponding row of memory cells in the memory bank;
• and
• applying a second supply voltage to word lines of the memory bank while the memory bank is not being accessed, wherein each of the word lines applies the second supply voltage to gates of access transistors in a corresponding row of memory cells in the memory bank, and wherein the first supply voltage turns off memory cells of the memory bank harder than the second supply voltage.

A method of operating a memory system comprising a plurality of memory banks comprising:

• applying a first supply voltage to non-selected word lines of memory banks being accessed, whereby the first supply voltage is applied to gates of access transistors of memory cells connected to the non-selected word lines in the memory banks being accessed;
• and
• applying a second supply voltage to word lines of memory banks not being accessed, whereby the second supply voltage is applied to gates of access transistors of memory cells in the memory banks not being accessed, wherein the first supply voltage turns off memory cells of the memory banks harder than the second supply voltage.