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US 8,526,264 B2Granted
Partial write on a low power memory architecture
AssigneeSTMicroelectronics International N.V.
InventorsAnuj Parashar, Marc Vernet
Life of this patent
Estimating the term…
Abstract
A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.
Claims21
A memory comprising:
- memory cells;
- data lines configured to provide data to and from the memory cells, the data lines being grouped into a plurality of blocks, each block comprising a plurality of the data lines;
- a plurality of block select lines, each block select line being associated with a respective one of the blocks;
- and
- selection circuitry for selecting the block in response to a respective block select line, the memory being configured to perform a memory operation using a selected bit line block,
- wherein the selection circuitry is configured to connect the selected bit line block to selected bit lines in response to a type of memory operation to be carried out.
3 more elements
A method comprising:
- selecting a data line block from a plurality of data line blocks in response to a block select signal associated with the data line block, each data line block comprising a plurality of data lines;
- and
- performing a memory operation using a selected block of bit lines;
- and
- connecting the selected block of bit lines to selected bit lines in response to a type of memory operation to be carried out.
2 more elements
A memory comprising:
- memory cells;
- data lines configured to provide data to and from the memory cells, the data lines being grouped into a plurality of blocks, each block comprising a plurality of the data lines;
- a plurality of block select lines, each block select line being associated with a respective one of the blocks;
- and
- selection circuitry for selecting the block in response to a respective block select line, the memory being configured to perform a memory operation using a selected bit line block,
- wherein the selection circuitry is further configured to connect the block to the memory interface in response to the block select line and a type of memory operation to be carried out.
3 more elements
A memory comprising:
- memory cells;
- data lines configured to provide data to and from the memory cells, the data lines being grouped into a plurality of blocks, each block comprising a plurality of the data lines;
- a plurality of block select lines, each block select line being associated with a respective one of the blocks;
- selection circuitry for selecting the block in response to a respective block select line, the memory being configured to perform a memory operation using a selected bit line block;
- and
- block select generation circuitry in a boot strap area of the memory for generating a block select signal to the block select line based on a memory instruction.
3 more elements
Dependencies are inferred from the claim text.