Back to results
US 8,526,263 B2Granted
Multi-layered memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsJaechul Park, Keewon Kwon, Youngsoo Park, Seunghoon Lee, Seungeon Ahn
Life of this patent
Estimating the term…
Abstract
A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array.
Claims19
A multi-layered memory device, comprising:
- a plurality of memory groups stacked on each other, each memory group including,
- a memory unit, and
- an active circuit unit configured to control the memory unit, wherein
- the active circuit unit includes at least one of a column decoder and a row decoder,
- the column decoder includes a first column decoder circuit at a first side of the active circuit unit and a second column decoder circuit at a second side of the active circuit unit,
- the first and second sides of the active circuit unit are opposite each other,
- the row decoder includes a first row decoder circuit at a third side of the active circuit unit and a second row decoder circuit at a fourth side of the active circuit unit, and
- the third and fourth sides of the active circuit unit are opposite to each other.
5 more elements
A multi-layered memory device, comprising:
- a plurality of memory groups stacked on each other, each memory group including,
- a memory unit, and
- an active circuit unit configured to control the memory unit, wherein
- the active circuit unit includes a first active circuit unit having a column decoder and a second active circuit unit having a row decoder, the memory unit being connected to each of the first active circuit unit and the second active circuit unit,
- the column decoder includes a first column decoder circuit at a first side of the active circuit unit and a second column decoder circuit at a second side of the active circuit unit,
- the first and second sides of the active circuit unit are opposite each other
- the row decoder includes a first row decoder circuit at a third side of the active circuit unit and a second row decoder circuit at a fourth side of the active circuit unit, and
- the third and fourth sides of the active circuit unit are opposite to each other.
5 more elements
Dependencies are inferred from the claim text.