Integrated circuit memory power supply
AssigneeThe Regents of the University of Michigan
InventorsGregory Kengho Chen, Dennis Michael Sylvester, David Theodore Blaauw
Life of this patent
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Abstract
An integrated circuit memory 2 is provided with an array of memory cells 4 and power supply circuitry 10, 12. Detected operating errors in malfunctioning memory cells 14 are identified using a built-in-self-test controller 34. The power supply circuitry 10, 12 is then configured to alter the voltage supply to the malfunctioning memory cells 14 in an attempt to correct their operation. The voltage supply of the row containing the malfunctioning memory cell and the column containing the malfunctioning memory cell may both be altered. The voltage alteration may be an increase or a decrease in voltage supply depending upon the nature of the malfunction detected.
Claims20
An integrated circuit memory comprising:
- an array of memory cells;
- and
- power supply circuitry coupled to said array to provide a voltage source to said array;
- wherein
- said power supply circuitry is configured to respond to a detected operating error in a malfunctioning memory cell of said array and to select at least one group of memory cells within said array, said group including said malfunctioning memory cell, and to alter, in response to said detected operating error, a voltage supply voltage to a source or drain terminal of at least one transistor of respective memory cells within said at least one group of memory cells to a voltage level at which said malfunctioning memory cell continues to operate, and to retain the altered voltage supply voltage during continued operation of the array to overcome said detected operating error.
An integrated circuit memory comprising:
- an array of memory cells;
- and
- power supply means for providing a voltage source to said array;
- wherein said power supply means is responsive to a detected operating error in a malfunctioning memory cell of said array and selecting at least one group of memory cells within said array, said group including said malfunctioning memory cell, said power supply means altering, in response to said detected operating error, the voltage of said voltage source to a source or drain terminal of at least one transistor of respective memory cells within said at least one group of memory cells to a voltage level at which said malfunctioning memory cell continues to operate and retaining the altered voltage during continued operation of the array to overcome said detected operating error.
A method of operating an integrated circuit memory having an array of memory cells and power supply circuitry coupled to said array to provide a voltage source to said array, said method comprising the steps of:
- detecting an operating error in a malfunctioning memory cell of said array;
- selecting at least one group of memory cells extending through said array, said group including said malfunctioning memory cell;
- and
- altering, in response to said detected operating error, the voltage of a voltage supply to a source or drain terminal of at least one transistor of respective memory cells within said at least one group of memory cells to a voltage level at which said malfunctioning memory cell continues to operate and retaining the altered voltage during said continued operation of the array to overcome said operating error.
Dependencies are inferred from the claim text.