Single-ended sense amplifier with read-assist

A sense amplifier, comprising:

• a precharge device coupled to an equalizer device, wherein the precharge device and the equalizer device turn off in an evaluation phase;
• a first node coupled to the equalizer, a source follower device, a set device, and an input of an inverting amplifier, responsive to receiving a set signal to turn on the set device and a read bit line signal that is discharging through a read stack path of the memory to ground and responsive to the read bit line signal discharging below a first predesigned voltage level, drops below a second predesigned voltage level;
• a second node coupled to an output of the inverting amplifier, wherein the second node starts a transition to a HIGH state due to a switching point of the inverting amplifier;
• and
• a read assist device coupled to the output of the inverting amplifier and the source follower device, wherein the read assist device turns on in response to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW state is output onto a global bit line.

A memory comprising:

• a set of memory cells;
• and
• a sense amplifier coupled to the set of memory cells, wherein the sense amplifier comprises:
• a precharge device coupled to an equalizer device, wherein the precharge device and the equalizer device turn off in an evaluation phase;
• a first node coupled to the equalizer, a source follower device, a set device, and an input of an inverting amplifier, wherein, responsive to receiving a set signal to turn on the set device and a precharged voltage level read bit line signal from one or more of the set of memory cells, a precharged voltage level of the first node remains above a switching point of the inverting amplifier such that a second node coupled to the output of the inverting amplifier is in a LOW state;
• and
• a keeper device coupled to an output of the inverting amplifier and a global bit line, wherein the keeper device turns on in response to receiving a LOW signal from the inverting amplifier and pulls up the voltage at the first node so that a HIGH signal is output onto a global bit line.

A memory comprising:

• a set of memory cells;
• and
• a sense amplifier coupled to the set of memory cells, wherein the sense amplifier comprises:
• a precharge device coupled to an equalizer device, wherein the precharge device and the equalizer device turn off in an evaluation phase;
• a first node coupled to the equalizer, a source follower device, a set device, and an input of an inverting amplifier, responsive to receiving a set signal to turn on the set device and a read bit line signal that is discharging through a read stack path of one or more of the set of memory cells to ground and responsive to the read bit line signal discharging below a first predesigned voltage level, drops below a second predesigned voltage level;
• a second node coupled to an output of the inverting amplifier, wherein the second node starts a transition to a HIGH state due to a switching point of the inverting amplifier;
• and
• a read assist device coupled to the output of the inverting amplifier and the source follower device, wherein the read assist device turns on in response to receiving HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW state is output onto a global bit line.