Method of screening static random access memories for pass transistor defects
AssigneeTexas Instruments Incorporated
InventorsBeena Pious, Jayesh C. Raval, Wah Kit Loh, Stanton Petree Ashburn
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Abstract
A method of screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells. A write of the opposite data state is then performed, followed by a read of the memory cells. The process is repeated for the opposite data state.
Claims20
A method of testing a solid-state read/write memory cell, the memory cell comprising a first inverter comprised of complementary load and driver transistors having their drains connected together at a first storage node and having their gates connected together, the memory cell further comprising a first pass transistor having a source/drain path connected between the first storage node and a first bit line, and having a gate receiving a word line signal, the method comprising:
- with the first storage node at a first logic level so that the load transistor of the first inverter is in an on state, applying a forward back-bias voltage to a load transistor of the first inverter;
- then placing a second logic level at the first bit line and energizing the word line signal;
- then de-energizing the word line signal;
- and
- then reading the memory cell.
A method of testing an array of memory cells arranged in rows and columns, each column of memory cells associated with a first and second bit lines, each memory cell comprising first and second cross-coupled CMOS inverters with outputs driving first and second storage nodes, each inverter comprised of complementary load and driver transistors, each memory cell further comprising a first pass transistor with a source/drain path connected between the first storage node and the first bit line for its column, and a second pass transistor with a source/drain path connected between the second storage node and the second bit line for its column, the gates of the first and second pass transistors receiving a word line signal for its row, the method comprising, for each memory cell in the array:
- writing the memory cell to a first logic state;
- then applying a forward back-bias to each of the load transistors of the memory cell;
- driving the first and second bit lines, for the column containing the memory cell, to voltages corresponding to the second logic state;
- then energizing the word line signal for the row containing the memory cell;
- then de-energizing the word line signal for the row containing the memory cell;
- and
- then reading the memory cell to determine its logic state.
Dependencies are inferred from the claim text.