Quiescent testing of non-volatile memory array
AssigneeSeagate Technology LLC
InventorsHai Li, Yiran Chen, Alan Xuguang Wang, Haiwen Xi, Wenzhong Zhu, Andreas K. Roelofs
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Abstract
A method and apparatus for testing an array of non-volatile memory cells, such as a spin-torque transfer random access memory (STRAM). In some embodiments, an array of memory cells having a plurality of unit cells with a resistive sense element and a switching device has a row decoder and a column decoder connected to the plurality of unit cells. A test circuitry sends a non-operational test pattern through the array via the row and column decoders with a quiescent supply current to identify defects in the array of memory cells.
Claims17
A memory device comprising:
- a memory array having a plurality of unit cells with a resistive sense element and a switching device;
- a row decoder connected to the plurality of unit cells;
- a column decoder connected to the plurality of unit cells;
- and
- a test circuit which establishes a non-operational configuration of the array via the row and column decoders by powering the array off, isolating the unit cells to be tested, and then powering the array on before a first test pattern with a first sensitivity is sent with a quiescent supply current to identify a first type and location of defects in the memory array and in response to the identified first type of defects a second test pattern with a second sensitivity different from the first sensitivity is chosen and sent with the quiescent supply current to identify a second type and location of defects from the same memory array, the first and second sensitivities respectively computed as a ratio of a difference between a faulty current and a nonfaulty current compared to the nonfaulty current.
A method comprising:
- providing a memory array having a plurality of unit cells with a resistive sense element and a switching device, wherein a row decoder and column decoder are connected to the plurality of unit cells;
- and
- testing the array with a test circuit that establishes a non-operational configuration of the array via the row and column decoders by powering the array off, isolating the unit cells to be tested, and then powering the array on before at least two test patterns are successively sent with a quiescent supply current to differentiate between at least first and second types and locations of defects in the same memory array, each test pattern selected in response to a previously identified type of defect result of the immediately preceding test pattern, the at least two test patterns each having different sensitivities computed as a ratio of a difference between a faulty current and a nonfaulty current compared to the nonfaulty current.
An apparatus comprising:
- a memory array having a plurality of unit cells with a resistive sense element and a switching device connected to row and column decoders;
- and
- a test circuit which establishes a non-operational configuration of the array via the row and column decoders, the test circuit configured to identify one or more particular types and locations of defects in the same memory array with more than one test patterns each having different sensitivities, at least one test pattern sensitivity selected in response to a previously identified type of defects, each sensitivity computed as a ratio of a difference between a faulty current and a nonfaulty current compared to the nonfaulty current.
Dependencies are inferred from the claim text.