Semiconductor apparatus, method for delaying signal thereof, stacked semiconductor memory apparatus, and method for generating signal thereof
AssigneeSK hynix Inc.
InventorsHeat Bit Park, Kee Teok Park
Life of this patent
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Abstract
The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal.
Claims26
A stacked semiconductor memory apparatus comprising:
- a master chip;
- and
- a plurality of slave chips,
- wherein the plurality of slave chips are configured to receive an input signal from the master chip in common, and include variable delay units configured to generate an output signal by variably delaying the input signal based on a reference delay value and a process delay value, respectively,
- wherein the reference delay value varies in a fashion that is relatively insensitive to process, voltage, and temperature (PVT) variation, and the process delay value varies in a fashion that is relatively more sensitive to process, voltage, and temperature (PVT) variation than the reference delay value.
A method for generating a signal of a stacked semiconductor memory apparatus, comprising the steps of:
- transmitting by a master chip a first timing signal to a plurality of slave chips;
- comparing by each slave chip a reference delay value with a process delay value, wherein the reference delay value varies in a fashion that is relatively insensitive to process, voltage, and temperature (PVT) variation, and the process delay value varies in a fashion that is relatively more sensitive to process, voltage, and temperature (PVT) variation than the reference delay value;
- and
- generating by each slave chip a delay timing signal by variably delaying the first timing signal based on a result obtained by comparing the reference delay value with the process delay value.
A stacked semiconductor memory apparatus comprising:
- a master chip;
- and
- a plurality of slave chips,
- wherein the plurality of slave chips are configured to receive an input signal from the master chip, and
- wherein each slave chip comprises:
- a first delay circuit having a delay value unrelated to a process;
- a second delay circuit having a delay value related to the process;
- and
- a delay compensation circuit configured to compare the delay value unrelated to the process with the delay value related to the process and compensate for a delay value of the input signal.
Dependencies are inferred from the claim text.