US 8,526,250 B2 · Address delay circuit of semiconductor memory apparatus

Abstract

An address delay circuit of a semiconductor memory apparatus includes a first group control pulse generation unit configured to generate a first control pulse after input of a first group column address strobe pulse and passage of a time corresponding to a first set multiple of one cycle of a clock, a second group control pulse generation unit configured to generate a second control pulse after input of a second group column strobe address pulse and passage of a time corresponding to a second set multiple of the one cycle of the clock, a first address storage unit configured to receive and store a first group external address in response to the first control pulse, and output a first group internal address, and a second address storage unit configured to receive and store a second group external address in response to the second control pulse, and output a second group internal address.

Claims16

Dependent claims

An address delay circuit of a semiconductor memory apparatus, comprising:

a first group control pulse generation unit configured to generate a first control pulse after input of a first group column address strobe pulse and passage of a time corresponding to a first set multiple of one cycle of a clock;
a second group control pulse generation unit configured to generate a second control pulse after input of a second group column strobe address pulse and passage of a time corresponding to a second set multiple of the one cycle of the clock;
a first address storage unit configured to receive and store a first group external address in response to the first control pulse, and output a first group internal address;
and
a second address storage unit configured to receive and store a second group external address in response to the second control pulse, and output a second group internal address.

2 more elements

An address delay circuit of a semiconductor memory apparatus, comprising:

a first group control pulse generation unit configured to generate a first control pulse when a first group column address strobe pulse is input and one cycle of a clock passes, and generate a second control pulse when a first set cycle of the clock passes after the first group column address strobe pulse is input;
a second group control pulse generation unit configured to generate a third control pulse when a second group column strobe address pulse is input and the one cycle of the clock passes, and generate a fourth control pulse when a second set cycle of the clock passes after the second group column address strobe pulse is input;
a first address storage unit configured to receive, store and output a first group external address, wherein the first address storage unit operates in response to the first control pulse;
a second address storage unit configured to receive and store output of the first address storage unit in response to the second control pulse, and output a first group internal address;
a third address storage unit configured to receive, store and output a second group external address, wherein the third address storage unit operates in response to the third control pulse;
and
a fourth address storage unit configured to receive and store output of the third address storage unit in response to the fourth control pulse, and output a second group internal address.

4 more elements

An address delay circuit of a semiconductor memory apparatus, comprising:

a first group control pulse generation unit including a first flip-flop configured to receive a first group column address strobe pulse and generate a first control pulse, and second and third flip-flops configured to receive output of the first flip-flop and generate a second control pulse, wherein the second flip-flop and the third flip-flop are serially connected to each other;
a second group control pulse generation unit including a fourth flip-flop configured to receive a second group column address strobe pulse and generate a third control pulse, and fifth and sixth flip-flops configured to receive output of the fourth flip-flop and generate a fourth control pulse, wherein the fifth flip-flop and the sixth flip-flop are serially connected to each other;
a first address storage unit including a seventh flip-flop configured to receive, store and output a first group external address, wherein the seventh flip-flop operates in response to the first control pulse;
a second address storage unit including an eighth flip-flop configured to receive and store output of the first address storage unit in response to the second control pulse, and output a first group internal address;
a third address storage unit including a ninth flip-flop configured to receive, store and output a second group external address, wherein the ninth flip-flop operates in response to the third control pulse;
and
a fourth address storage unit including a tenth flip-flop configured to receive and store output of the third address storage unit in response to the fourth control pulse, and output a second group internal address.

4 more elements

Dependencies are inferred from the claim text.

Address delay circuit of semiconductor memory apparatus

Life of this patent

Address delay circuit of semiconductor memory apparatus

Life of this patent

Abstract

Claims16