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US 8,526,246 B2Granted
Write circuitry for hierarchical memory architectures
AssigneeSTMicroelectronics International N.V.
InventorsSiddharth Gupta, Nitin Jain, Anand Mishra
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Abstract
A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.
Claims8
A global input and output circuitry comprising:
- a global clock generation circuitry to generate a global write clock signal;
- and
- a global write circuitry coupled to the global clock generation circuitry, wherein the global write circuitry is configured to transfer a write-data, the global write circuitry comprising:
- a full transmission gate to facilitate transfer of the write-data based on the global write clock signal;
- a plurality of global sub-write circuitries, each global sub-write circuitry comprising:
- a storage element coupled to the full transmission gate, wherein the storage element stores the write-data;
- and
- a decoupling circuit configured to disable the full transmission gate based on the write-data stored in the storage element.
5 more elements
Dependencies are inferred from the claim text.