Non-volatile semiconductor memory device capable of improving failure-relief efficiency

A non-volatile semiconductor storage device comprising:

• a memory cell array comprising a set of plurality of NAND strings as a physical block, the plurality of NAND strings respectively including a plurality of memory cells and sharing a plurality of word lines respectively connected to the plurality of memory cells;
• and
• a row decoder configured to drive the plurality of word lines,
• wherein the physical block is divided into a plurality of first logical blocks,
• wherein the row decoder comprises:
• a plurality of latch circuits provided respectively corresponding to the plurality of first logical blocks, the plurality of latch circuits configured to store a flag indicating a failure when the failure exists in the corresponding first logical block;
• and
• a drive circuit configured to inhibit driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which selected word lines belong, and the drive circuit configured to allow driving of the word lines belonging to the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong.