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US 8,526,238 B2Granted
Memory arrays and methods of operating memory
AssigneeMicron Technology, Inc.
InventorsViolante Moschiano, Giovanni Santin
Life of this patent
Estimating the term…
Abstract
Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.
Claims26
A method of operating a memory device, comprising:
- initiating programming of a page of the memory;
- precharging a plurality of common lines, each common line connected to all page buffers of a respective rank of page buffers corresponding to the page of the memory;
- discharging each precharged common line that has at least one page buffer connected thereto that is selectively coupled to a memory cell that fails verification.
A method of identifying failed programming in a memory array, comprising:
- precharging a plurality of common lines, each common line connected to a respective plurality of page buffers of the same rank corresponding to a page of memory;
- enabling a program transistor to discharge a respective common line if a memory cell selectively coupled to a page buffer connected to the common line fails programming.
A memory device, comprising:
- an array of memory cells;
- circuitry for control and/or access of the array of memory cells;
- and
- a data detector comprising:
- a plurality of common lines, each common line connected to a respective rank of page buffers corresponding to a page of the array of memory cells;
- and
- a plurality of pass/fail circuits, each pass/fail circuit connected to a respective one of the plurality of common lines.
4 more elements
A memory device, comprising:
- an array of memory cells;
- and
- circuitry for control and/or access of the array of memory cells, the control circuitry configured to perform a method comprising:
- initiating programming of a page of the memory;
- precharging a plurality of common lines, each common line connected to all page buffers of a respective rank of page buffers corresponding to the page of the memory;
- discharging each precharged common line that has at least one page buffer connected thereto that is selectively coupled to a memory cell that fails verification.
3 more elements
A memory, comprising:
- an array of memory cells;
- circuitry for control and/or access of the array of memory cells;
- and
- a data detector, comprising:
- a plurality of common lines, each common line connected to each of a plurality of page buffers of a respective rank corresponding to a page of the array of memory cells;
- a plurality of check transistors, a check transistor for each page buffer, each check transistor connected to one of the plurality of common lines through one of a plurality of program transistors;
- a plurality of latches, a latch connected to the gate of each program transistor;
- and
- a plurality of pass/fail circuits, a pass/fail circuit connected to each of the plurality of common lines.
6 more elements
Dependencies are inferred from the claim text.