Back to results
US 8,526,227 B2Granted
Phase change memory word line driver
AssigneeMosaid Technologies Incorporated
InventorHong Beom Pyeon
Life of this patent
Estimating the term…
Abstract
A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.
Claims20
A method for improving sub-word line response comprising:
- generating a variable substrate bias determined by at least one user parameter;
- applying the variable substrate bias to a sub-word line driver in a selected sub-block of a memory;
- and
- minimizing voltage disturbance on a sub-word line in communication with the sub-word line driver by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.
1 more element
An adaptable sub-word line driver comprising:
- a sub-word line driver in communication with a plurality of memory cells in a memory, the sub-word line driver including a transistor with a variable substrate bias voltage, a source of the transistor being in communication with a ground potential and a drain of the transistor in communication with a sub-word line, the transistor being formed in a P-well and being in communication with the variable substrate bias voltage;
- and
- a variable substrate bias voltage generator including at least one resistor in series with a bias resistor, each resistor being in parallel with a shunting transistor controlled by a trim value, the at least one resistor and the bias resistor dividing a bias voltage to produce the variable substrate bias voltage.
A memory system comprising:
- a plurality of sub-arrays of a memory, each sub-array including a plurality of memory cells in communication with at least one sub-word line driver, the at least one sub-word line driver of each sub-array being formed in a P-well and being in communication with a variable substrate bias voltage;
- a variable substrate bias voltage generator including at least one resistor in series with a bias resistor, each resistor being in parallel with a shunting transistor controlled by a trim value, the at least one resistor and the bias resistor dividing a bias voltage to produce the variable substrate bias voltage;
- and
- an address decoder selecting one of the plurality of sub-arrays, the address decoder enabling communication with the variable substrate bias voltage generator and the selected one of the plurality of sub-arrays.
1 more element
Dependencies are inferred from the claim text.