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US 8,526,220 B2Granted
Complementary SOI lateral bipolar for SRAM in a low-voltage CMOS platform
AssigneeInternational Business Machines Corporation
InventorsJin Cai, Tak H. Ning
Life of this patent
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Abstract
An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.
Claims20
A memory cell comprising:
- a semiconductor-on-insulator (SOI) substrate;
- a first set of lateral bipolar transistors fabricated on the SOI substrate, the first set of lateral bipolar transistors forming a first inverter having a first output terminal configured to invert a first input signal at a first input terminal;
- and
- a second set of lateral bipolar transistors fabricated on the SOI substrate, the second set of lateral bipolar transistors forming a second inverter having a second output terminal configured to invert a second input signal at a second input terminal;
- wherein the first inverter is cross coupled to the second inverter such that the first input terminal is electrically coupled to the second output terminal and the second input terminal is electrically coupled to the first output terminal.
2 more elements
A method for fabricating a memory cell, the method comprising:
- depositing a semiconductor-on-insulator (SOI) substrate;
- constructing a first set of lateral bipolar transistors on the SOI substrate;
- coupling the first set of lateral bipolar transistors to form a first inverter having a first output terminal configured to invert a first input signal at a first input terminal;
- constructing a second set of lateral bipolar transistors on the SOI substrate;
- coupling the second set of lateral bipolar transistors to form a second inverter having a second output terminal configured to invert a second input signal at a second input terminal;
- and
- cross coupling the first inverter to the second inverter such that the first input terminal is electrically coupled to the second output terminal and the second input terminal is electrically coupled to the first output terminal.
4 more elements
A memory array comprising:
- a semiconductor-on-insulator (SOI) substrate;
- and
- a plurality of memory cells, each of the memory cells including:
- a first set of lateral bipolar transistors fabricated on the SOI substrate, the first set of lateral bipolar transistors forming a first inverter having a first output terminal configured to invert a first input signal at a first input terminal;
- and
- a second set of lateral bipolar transistors fabricated on the SOI substrate, the second set of lateral bipolar transistors forming a second inverter having a second output terminal configured to invert a second input signal at a second input terminal;
- wherein the first inverter is cross coupled to the second inverter such that the first input terminal is electrically coupled to the second output terminal and the second input terminal is electrically coupled to the first output terminal.
4 more elements
Dependencies are inferred from the claim text.