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US 8,526,210 B2Granted
Semiconductor device with OTP memory cell
AssigneeSK hynix Inc.
InventorTae Hoon Kim
Life of this patent
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Abstract
A semiconductor device with an OTP memory cell includes a first MOS transistor having a first gate terminal connected to a first line, and a first terminal connected to a first node, a second MOS transistor having a second gate terminal connected to a second line, and a first terminal connected to the first node, and a third MOS transistor having a gate terminal connected to a three line, and a first terminal of the third MOS transistor connected to the first node.
Claims20
A semiconductor device with a one-time programmable (OTP) memory cell, comprising:
- a first MOS transistor having a first gate terminal connected to a first line, a first terminal of the first MOS transistor connected to a first node, and a second terminal of the first MOS transistor connected to a bias voltage line;
- a second MOS transistor having a second gate terminal connected to a second line, a first terminal of the second MOS transistor connected to the first node, and a second terminal of the second MOS transistor connected to a bias voltage line;
- and
- a third MOS transistor having a third gate terminal connected to a third line, a first terminal of the third MOS transistor connected to the first node, and a second terminal of the third MOS transistor connected to a ground terminal,
- wherein a current path is formed in a programming mode by breaking down an insulation film of one of the first gate terminal and the second gate terminal so that a current flows through one of the first gate terminal and the second gate terminal to the first node.
2 more elements
A semiconductor device with a plurality of OTP memory cells, comprising:
- a plurality of bias voltage lines connected to first and second MOS transistors in each corresponding OTP memory cell;
- a plurality of lines arranged so that a corresponding pair of the plurality of lines are connected to the first and the second MOS transistors in each corresponding OTP memory cell;
- a plurality of three lines connected to a third MOS transistor in each corresponding OTP memory cell;
- a plurality of line sense amplifiers configured to sense and amplify data signals provided to the plurality of lines;
- and
- wherein each OTP memory cell comprises:
- the first MOS transistor having a first gate terminal connected to a first line of the corresponding pair of lines, a first terminal of the first MOS transistor connected to a first node, and a second terminal of the first MOS transistor connected to a corresponding bias voltage line;
- the second MOS transistor having a second gate terminal connected to a second line of the corresponding pair of lines, a first terminal of the second MOS transistor connected to the first node, and a second terminal of the second MOS transistor connected to the corresponding bias voltage line connected to the first MOS transistor;
- and
- the third MOS transistor having a gate terminal connected to a corresponding three line, and a first terminal of the third MOS transistor connected to the first node, and the second terminal of the third MOS transistor connected to ground.
7 more elements
Dependencies are inferred from the claim text.