Systems and methods for signal polarity determination

A head polarity detection circuit, the circuit comprising:

• a first computation circuit operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum;
• a first pattern detection circuit operable to resolve the first subset of the series of data samples to a first set of binary values representing the first subset of the series of data samples and comparing the first set of binary values to a defined pattern, wherein the defined pattern is identified in the first subset of the series of data samples;
• a second computation circuit operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum, wherein the first phase is more than ninety degrees offset from the second phase;
• a second pattern detection circuit operable to resolve the second subset of the series of data samples to a second set of binary values representing the second subset of the series of data samples and comparing the second set of binary values to the defined pattern, wherein the defined pattern is identified in the second subset of the series of data samples;
• and
• an inversion determination circuit operable to determine a signal polarity based at least in part on a difference between the first sum and the second sum.

A storage device, the storage device comprising:

• a storage medium;
• a head assembly disposed in relation to the storage medium and operable to generate an analog input corresponding to information on the storage medium;
• a head polarity determination circuit including:
• a first computation circuit operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of the analog input to yield a first sum;
• a first pattern detection circuit operable to resolve the first subset of the series of data samples to a first set of binary values representing the first subset of the series of data samples and comparing the first set of binary values to a defined pattern, wherein the defined pattern is identified in the first subset of the series of data samples;
• a second computation circuit operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum, wherein the first phase is more than ninety degrees offset from the second phase;
• a second pattern detection circuit operable to resolve the second subset of the series of data samples to a second set of binary values representing the second subset of the series of data samples and comparing the second set of binary values to a defined pattern;
• and
• an inversion determination circuit operable to determine a polarity of the head assembly based at least in part on a difference between the first sum and the second sum.