Suspending column readout in image sensors

An image sensor comprising:

• a two-dimensional array of pixels, the array including a plurality of column outputs;
• an output circuit connected to each column output, wherein each output circuit is configured to operate concurrent sample and read operations;
• a column decoder electrically connected to each output circuit;
• an analog front end (AFE) circuit for processing pixel data;
• an AFE clock controller for transmitting an AFE clocking signal to the AFE circuit to effect processing of the pixel data;
• and
• a timing generator for outputting a column address sequence that is received by the column decoder, wherein during a sample operation the AFE clock controller suspends the output of the AFE clocking signal and the timing generator suspends the output of the column address sequence during the sample operation and resume the output of the AFE clocking signal and the column address sequence coincident with or after the end of the sample operation and wherein the AFE clocking signal and the column address sequence are suspended for a predetermined number of clock periods.