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US 8,525,896 B2Granted
Solid-state imaging apparatus
AssigneeCanon Kabushiki Kaisha
InventorsAkira Okita, Masaaki Minowa
Life of this patent
Estimating the term…
Abstract
A solid-state imaging apparatus according to the present invention is characterized in that a reset gate voltage VresH to be applied to a gate of a reset MOS transistor is lower than a power supply voltage SVDD of a power supply to which drains of an amplifying MOS transistor and the reset MOS transistor are connected.
Claims16
A solid-state imaging apparatus comprising:
- a plurality of pixels, each of the pixels comprising:
- a photoelectric converter configured to perform photoelectric conversion of incident light;
- an amplifying MOS (metal oxide semiconductor) transistor configured to output a signal based on a charge generated by the photoelectric converter;
- and
- a reset MOS transistor configured to reset potential of a gate of the amplifying MOS transistor to a voltage determined by a voltage of a gate of the reset MOS transistor and a threshold voltage of the reset MOS transistor,
- wherein the amplifying MOS transistor is an N-type buried-channel MOS transistor,
- the reset MOS transistor is arranged such that a voltage to be applied to the gate of the reset MOS transistor for setting the reset MOS transistor in a conduction state is lower than a voltage to be applied to a drain of the reset MOS transistor, and
- a source of the reset MOS transistor is electrically connected to the gate of the amplifying MOS transistor.
5 more elements
A solid-state imaging apparatus comprising:
- a plurality of pixels, each of the pixels comprising:
- a photoelectric converter configured to perform photoelectric conversion of incident light;
- an amplifying MOS transistor configured to output a signal based on a charge generated by the photoelectric converter;
- and
- a reset MOS transistor configured to reset potential of a gate of the amplifying MOS transistor to a voltage determined by a voltage of a gate of the reset MOS transistor and a threshold voltage of the reset MOS transistor,
- wherein the amplifying MOS transistor is a P-type buried-channel MOS transistor,
- the reset MOS transistor is arranged such that a voltage to be applied to the gate of the reset MOS transistor for setting the reset MOS transistor in a conduction state is higher than a voltage to be applied to a drain of the reset MOS transistor, and
- a source of the reset MOS transistor is electrically connected to the gate of the amplifying MOS transistor.
5 more elements
A solid-state imaging apparatus comprising:
- a plurality of pixels, each of the pixels comprising:
- a photoelectric converter configured to perform photoelectric conversion of incident light;
- an amplifying MOS transistor configured to output a signal based on a charge generated by the photoelectric converter;
- and
- a reset MOS transistor configured to reset a gate potential of the amplifying MOS transistor,
- wherein the amplifying MOS transistor is an N-type buried-channel MOS transistor, and the reset MOS transistor is arranged such that a threshold voltage (Vth_res) of the reset MOS transistor, a voltage (VDD) to be applied to a gate of the reset MOS transistor for setting the reset MOS transistor in a conduction state, a voltage (SVDD) to be applied to a drain of the amplifying MOS transistor, and a threshold voltage (Vth_sf) of the amplifying MOS transistor satisfy the following expression:
- Vth—res≧VDD−SVDD−Vth—sf.
4 more elements
A solid-state imaging apparatus comprising:
- a plurality of pixels, each of the pixels comprising:
- a photoelectric converter configured to perform photoelectric conversion of incident light;
- an amplifying MOS transistor configured to output a signal based on a charge generated by the photoelectric converter;
- and
- a reset MOS transistor configured to reset a gate potential of the amplifying MOS transistor,
- wherein the amplifying MOS transistor is a P-type buried-channel MOS transistor, and the reset MOS transistor is arranged such that a threshold voltage (Vth_res) of the reset MOS transistor, a voltage (VSS) to be applied to a gate of the reset MOS transistor for setting the reset MOS transistor in a conduction state, a voltage (SVSS) to be applied to a drain of the amplifying MOS transistor, and a threshold voltage (Vth_sf) of the amplifying MOS transistor satisfy the following expression:
- Vth—res≦VSS−SVSS−Vth—sf.
4 more elements
Dependencies are inferred from the claim text.