Thermal management of graphics processing units

A method for controlling a graphics processing unit (GPU) comprising:

• providing a raw clock signal;
• generating a divided version of the raw clock signal;
• providing a display controller the raw clock signal but not the divided version of the raw clock signal;
• providing a microprocessing engine a timing signal that selectively comprises the raw clock signal or the divided version of the raw clock signal;
• varying a composition of the timing signal based at least in part on a GPU_ENABLE signal, wherein the GPU_ENABLE comprises a pulse width modulated (PWM) signal or a register setting, or both;
• executing operations on the microprocessing engine at a reduced rate based at least in part on the timing signal;
• and
• operating the display controller at a rate of execution based at least in part on the raw clock signal.

A computer system comprising:

• a central processing unit (CPU);
• a graphics processing unit (GPU) coupled to the CPU, wherein the GPU is configured to generate image data;
• one or more displays coupled to the GPU, wherein the one or more displays are configured to display the image data;
• and
• a power regulation circuit coupled to the GPU, wherein the power regulation circuit is configured to monitor a temperature of the GPU and to transmit a pulse width modulated (PWM) signal to the GPU to control power consumption of the GPU;
• wherein the GPU comprises:
• a display controller;
• a microprocessing engine coupled to the display controller;
• a clock circuit directly coupled to the display controller and to the microprocessing engine, the clock circuit comprising:
• an oscillation circuit directly coupled to the display controller, wherein the oscillation circuit is configured to provide only a raw clock signal to the display controller;
• a divider directly coupled to the oscillation circuit, wherein the divider is configured to generate a divided version of the raw clock signal;
• and
• a multiplexer directly coupled to the oscillation circuit, to the divider, and to the power regulation circuit, wherein the multiplexer is configured to selectively provide the raw clock signal or the divided version of the raw clock signal to the microprocessing engine as a timing signal based at least in part on the PWM signal from the power regulation circuit.