LCD panel driving circuit having transition slope adjusting means and associated control method

A liquid crystal display (LCD) panel, coupled to a display controller, the LCD panel comprising:

• a master source driver, for receiving a digital image signal in compliance with a first electrical specification from the display controller and converting the digital image signal to a gate driving signal and a slave source driving signal in compliance with a second electrical specification;
• a gate driver, for receiving the gate driving signal in compliance with the second electrical specification;
• and
• a slave source driver, for receiving the slave source driving signal in compliance with the second electrical specification,
• wherein, the master source driver, the slave source driver and the gate driver drive a thin-film transistor (TFT) array on the LCD panel according to the digital image signal, the slave source driving signal and the gate driving signal, respectively,
• wherein the master source driver comprises a main circuit and a conversion output unit, wherein the conversion output unit receives an output from the main circuit, and the conversion output unit comprises a plurality of buffers and at least one delay unit to adjust a transition slope of the output from the main circuit and produce the gate driving signal and the slave driving signal,
• wherein the first electrical specification is a transistor-transistor logic (TTL) specification or a complementary metal-oxide-semiconductor (CMOS) logic specification,
• wherein the main circuit is configured for receiving the digital image signal in compliance with the TTL specification or the CMOS logic specification and converting the digital image signal to another gate driving signal and another slave source driving signal in compliance with the TTL specification or the CMOS logic specification,
• wherein the conversion output unit is configured for receiving said another gate driving signal and said another slave source driving signal in compliance with the TTL specification or the CMOS logic specification, and converting said another gate driving signal and said another slave source driving signal to the gate driving signal and the slave source driving signal in compliance with the second electrical specification,
• wherein the conversion output unit comprises:
• a first buffer;
• a first delay unit;
• a second buffer, with an input end connected to an output end of the first delay unit;
• a second delay unit;
• a third buffer, with an input end connected to an output end of the second delay unit;
• and
• wherein the gate driving signal in compliance with the TTL specification or the CMOS logic specification is received at an input end of the first buffer, an input end of the first delay unit and an input end of the second delay unit, and the gate driving signal in compliance with the second electrical specification is outputted at an output end of the first buffer, the output end of the second buffer and the output end of the third buffer.