PLL frequency synthesizer

A phase locked loop frequency synthesizer, comprising:

• an oscillation section that includes a first capacitance element group made up of a plurality of variable capacitance elements and a second capacitance element group made up of a plurality of variable capacitance elements;
• and
• an oscillating frequency control section that controls an output frequency of the oscillation section by generating a phase error signal corresponding to a difference between a phase of an output signal of the oscillation section and a phase of a reference signal, controlling a capacitance value of the first capacitance element group using an integer part of the phase error signal, and controlling a capacitance value of the second capacitance element group using a fraction part of the phase error signal,
• wherein the phase locked loop frequency synthesizer comprises:
• a frequency characteristic adjusting section that generates an adjustment signal based on a result of a comparison between a difference between the value of the fraction part and an integer value closest to the value of the fraction part and a predetermined threshold;
• and
• a frequency characteristic shifting section provided in the oscillation section that shifts an oscillating frequency characteristic of the oscillation section based on the adjustment signal.