Clock frequency overshoot detection circuit
AssigneeFreescale Semiconductor, Inc.
InventorsGarima Sharda, Sunny Gupta
Life of this patent
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Abstract
An electronic circuit operating on a first clock signal includes a clock frequency overshoot detection circuit for detecting frequency overshoots in the first clock signal. The clock frequency overshoot detection circuit includes a shift register having an even number plurality of flip-flops. The flip-flops toggle to generate output bit patterns indicative of a frequency overshoot condition. A comparator connected to the shift register generates a comparison signal on detecting the frequency overshoot condition. A latch circuit connected to the comparator generates a frequency overshoot indication signal and the electronic circuit is shifted to a second (or safe) clock signal until the frequency of the first clock signal is rectified.
Claims20
A clock frequency overshoot detection circuit, comprising:
- a clock gating cell for receiving a first clock signal and generating a gated clock signal based on a count signal;
- a shift register connected to the clock gating cell and including at least two pairs of flip-flops, wherein each pair of flip-flops includes a set flip-flop and a reset flip-flop, and wherein an input terminal of each flip-flop is connected to an output terminal of a previous flip-flop and an output terminal of a last flip-flop is connected to an input terminal of a first flip-flop, and wherein the gated clock signal is provided to respective clock inputs of each of the flip-flops such that an output of each of the flip-flops toggles at each pulse of the gated clock signal, thereby generating an output bit pattern;
- a comparator, connected to the output terminals of each of the flip-flops, for generating a comparison signal;
- a latch circuit, connected to the comparator, and having a clock input for receiving the comparison signal and a data input terminal for receiving a predefined logic value, wherein the latch circuit outputs a frequency overshoot indication signal;
- and
- a binary counter, connected to the clock gating cell, for generating and providing the count signal to the clock gating cell.
An electronic circuit that receives a first clock signal from a clock generation circuit, comprising;
- a clock frequency overshoot detection circuit for detecting a frequency overshoot in the first clock signal, wherein the clock frequency overshoot detection circuit includes,
- a clock gating cell for receiving the first clock signal and generating a gated clock signal based on a count signal;
- a shift register connected to the clock gating cell and including at least two pairs of flip-flops, wherein each pair of flip-flops includes a set flip-flop and a reset flip-flop, and wherein an input terminal of each flip-flop is connected to an output terminal of a previous flip-flop and an output terminal of a last flip-flop is connected to an input terminal of a first flip-flop, and wherein the gated clock signal is provided to respective clock inputs of each of the flip-flops such that an output of each of the flip-flops toggles at each pulse of the gated clock signal, thereby generating an output bit pattern;
- a comparator, connected to the output terminals of each of the flip-flops, for generating a comparison signal;
- a latch circuit, connected to the comparator and having a clock input for receiving the comparison signal and a data input terminal for receiving a predefined logic value, wherein the latch circuit outputs a frequency overshoot indication signal;
- and
- a binary counter, connected to the clock gating cell, for generating and providing the count signal to the clock gating cell.
A clock frequency overshoot detection circuit, comprising:
- a clock gating cell for receiving a first clock signal and generating a gated clock signal based on a count signal;
- a 32-bit shift register connected to the clock gating cell and including sixteen pairs of flip-flops, wherein each of the sixteen pairs of flip-flops includes a set flip-flop and a reset flip-flop, and wherein an input terminal of each flip-flop is connected to an output terminal of a previous flip-flop and an output terminal of a last flip-flop is connected to an input terminal of a first flip-flop, and wherein the gated clock signal is provided to respective clock inputs of each of the flip-flops such that an output of each of the flip-flops toggles at each pulse of the gated clock signal, thereby generating an output 32-bit pattern;
- a comparator, connected to the output terminals of each of the flip-flops, for generating a comparison signal;
- a latch circuit, connected to the comparator and having a clock input for receiving the comparison signal and a data input terminal for receiving a predefined logic value, wherein the latch circuit outputs a frequency overshoot indication signal;
- and
- a binary counter, connected to the clock gating cell, for generating and providing the count signal to the clock gating cell.
Dependencies are inferred from the claim text.