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US 8,525,583 B2Granted
Circuit, an adjusting method, and use of a control loop
AssigneeAtmel Corporation
InventorsLutz Dathe, Matthias Vorwerk, Thomas Hanusch
Life of this patent
Estimating the term…
Abstract
A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.
Claims20
A circuit comprising:
- a CMOS circuit having NMOS field-effect transistors and having PMOS field-effect transistors;
- a first load device, wherein source terminals of the NMOS field-effect transistors of the CMOS circuit are connectable via the first load device to a first supply voltage;
- a second load device, wherein source terminals of the PMOS field-effect transistors of the CMOS circuit are connectable via the second load device to a second supply voltage;
- and
- an evaluation circuit configured to:
- evaluate a first source voltage at the source terminals of the NMOS field-effect transistors;
- evaluate a second source voltage at the source terminals of the PMOS field-effect transistors;
- determine whether a leakage current through the CMOS circuit is predominantly due to the NMOS field-effect transistors or the PMOS field-effect transistors;
- adjust, when a determination is made that the leakage current is predominately due to the PMOS field-effect transistors, a first voltage drop across the first load device;
- and
- adjust, when a determination is made that the leakage current is predominately due to the NMOS field-effect transistors, a second voltage drop across the second load device.
8 more elements
A method comprising:
- determining a first source voltage applied at source terminals of NMOS field-effect transistors of a CMOS circuit;
- determining a second source voltage applied at source terminals of PMOS field-effect transistors of the CMOS circuit;
- determining whether a leakage current through the CMOS circuit is predominantly due to the NMOS field-effect transistors or the PMOS field-effect transistors;
- adjusting, when a determination is made that the leakage current is predominately due to the PMOS field-effect transistors, a first voltage drop across a first load device, the first load device being connected to the source terminals of the NMOS field-effect transistor;
- and
- adjusting, when a determination is made that the leakage current is predominately due to the NMOS field-effect transistors, a second voltage drop across a second load device, the second load device being connected to the source terminals of the PMOS field-effect transistor.
3 more elements
An apparatus, comprising:
- means for determining a first source voltage applied at source terminals of NMOS field-effect transistors of a CMOS circuit;
- means for determining a second source voltage applied at source terminals of PMOS field-effect transistors of the CMOS circuit;
- means for determining whether a leakage current through the CMOS circuit is predominantly due to the NMOS field-effect transistors or the PMOS field-effect transistors;
- means for adjusting, when a determination is made that the leakage current is predominately due to the PMOS field-effect transistors, a first voltage drop across a first load device, the first load device being connected to the source terminals of the NMOS field-effect transistor;
- and
- means for adjusting, when a determination is made that the leakage current is predominately due to the NMOS field-effect transistors, a second voltage drop across a second load device, the second load device being connected to the source terminals of the PMOS field-effect transistor.
3 more elements
Dependencies are inferred from the claim text.