Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network

A method for synchronizing global clock signals within a 3D chip stack having two or more strata, the method comprising:

• providing on each of the two or more strata,
• a clock grid having a plurality of sectors for providing the global clock signals to various chip locations;
• a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers;
• and
• one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree;
• shorting together inputs of at least some of the plurality of clock buffers on each of the two or more strata using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

A clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata including a master stratum and non-master strata, the clock distribution network comprising:

• on each of the two or more strata,
• a clock grid having a plurality of sectors for providing the global clock signals to various chip locations;
• a multiple-level buffered clock tree having a plurality of sector clock buffers for driving the plurality of sectors, a plurality of relay clock buffers for distributing the global clock signals to the plurality of sector clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree;
• and
• wherein the one or more multiplexers on the master stratum drive the one or more multiplexers on all of the non-master strata.

A method for synchronizing global clock signals within a 3D chip stack having two or more strata, the method comprising:

• providing on each of the two or more strata,
• a clock grid having a plurality of sectors for providing the global clock signals to various chip locations;
• a multiple-level buffered clock tree having a plurality of sector clock buffers for driving the plurality of sectors, a plurality of relay clock buffers for distributing the global clock signals to the plurality of sector clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree;
• and
• driving the one or more multiplexers on all of the non-master strata using the one or more multiplexers on the master stratum.