Clock generation circuit
AssigneeIPGoal Microelectronics (SiChuan) Co., Ltd.
InventorsZhaolei Wu, Yalan Lv, Guosheng Wu
Life of this patent
Estimating the term…
Abstract
A clock generation circuit, includes a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator. The present invention has simple structure, small process variation, and lower cost, and is able to improve the accuracy of the clock with maximum possibility.
Claims19
A clock generation circuit, comprising:
- a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator, wherein the RS trigger outputs clock signals to an input control terminal of the first demux circuit and an input control terminal of the second demux circuit, when the first demux circuit is enabled, the capacitor is charged by the second current source, and when the second demux circuit is enabled, the capacitor is discharged by the second current source,
- wherein the resistance of the resistor is R, the first current source is proportional to
- 1
- R
- 2
- ,
- and the second current source is proportional to
- 1
- R
- .
A clock generation circuit, comprising:
- a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator, wherein the RS trigger outputs clock signals to an input control terminal of the first demux circuit and an input control terminal of the second demux circuit, when the first demux circuit is enabled, the capacitor is charged by the second current source, and when the second demux circuit is enabled, the capacitor is discharged by the second current source,
- wherein the first current source comprises a first field effect transistor (FET) MP1, a second FET MP2 connected to the first FET MP1, a ninth FET MN1 connected to the first FET MP1, a tenth FET MN2 connected to the second FET MP2, and a first resistor R1 connected to the tenth FET MN2, wherein the second FET MP2 is connected through a third FET MP3 to the first side of the resistor, the first resistor R1 is connected through an eleventh FET MN3 to the second side of the resistor.
A clock generation circuit, comprising:
- a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator, wherein the RS trigger outputs clock signals to an input control terminal of the first demux circuit and an input control terminal of the second demux circuit, when the first demux circuit is enabled, the capacitor is charged by the second current source, and when the second demux circuit is enabled, the capacitor is discharged by the second current source,
- wherein the first demux circuit comprises an eighth FET MP8, the second demux circuit comprises a sixteenth FET MN8 connected to the eighth FET MP8.
Dependencies are inferred from the claim text.