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US 8,525,567 B2Granted
Pipeline circuit, semiconductor device, and pipeline control method
AssigneeNEC Corporation
InventorAtsufumi Shibayama
Life of this patent
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AssigneeNEC Corporation
InventorAtsufumi Shibayama
Estimating the term…
Provided is a pipeline circuit capable of flexibly controlling clock frequencies regardless of whether a pipeline operation by a flow control is stopped or not, without significantly increasing a processing latency even if a clock frequency is decreased, and in response to performance requests for a processing throughput. Among P clocks (P is a positive integer), the phases of which are delayed in the order from a first clock to a P-th clock, for example, among six clocks of P0 to P5, two successive clocks, the phases of which are delayed from each other by a predetermined phase, are allocated to a plurality of stages, for example, five-stage pipeline buffers 32a to 32e, in the order from a previous stage to a subsequent stage, and also are allocated so that one clock signal having an identical phase is shared between two adjacent pipeline buffers.
A pipeline circuit comprising a plurality of stages of pipeline buffers, in which among P (P is a positive integer) clock signals from a first clock signal to a P-th clock signal, two successive clock signals whose phases are delayed each other by a predetermined phase are sequentially allocated to each of pipeline buffers from a pipeline buffer located at a previous stage of the pipeline circuit to a pipeline buffer located at a subsequent stage of the pipeline circuit, the clock signals being allocated so that two adjacent pipeline buffers share one clock signal having an identical phase among the two clock signals allocated to the two adjacent pipeline buffers, each of the pipeline buffers being operated by the two clock signals allocated to each of them, the P number of clock signals having phases delayed in the order from the first clock signal to the P-th clock signal.
A pipeline control method controlling a pipeline circuit comprising a plurality of stages of pipeline buffers, in which among P (P is a positive integer) clock signals from a first clock signal to a P-th clock signal, two successive clock signals whose phases are delayed each other by a predetermined phase are sequentially allocated to each of pipeline buffers from a pipeline buffer located at a previous stage of the pipeline circuit to a pipeline buffer located at a subsequent stage of the pipeline circuit, the clock signals being allocated so that two adjacent pipeline buffers share one clock signal having an identical phase among the two clock signals allocated to the two adjacent pipeline buffers, each of the pipeline buffers being operated by the two clock signals allocated to each of them, the P number of clock signals having phases delayed in the order from the first clock signal to the P-th clock signal.
Dependencies are inferred from the claim text.