US 8,525,566 B2Granted

Glitch hardened flop repeater

AssigneeOracle International Corporation

InventorsAnand Dixit, Robert P. Masleid

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Abstract

A repeater circuit is disclosed. The circuit includes an input stage configured to receive an input signal and a clock signal. An output stage is configured to drive an output signal on an output node to a first state responsive to a first transition of the input signal on the input node concurrent with a first phase of the clock signal. The input stage is configured to activate a first driver circuit of the output stage responsive to a first transition of the input signal. A reverse stage is configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, which is configured to be deactivated responsive to assertion of the first inhibit signal. Assertion of the first inhibit signal is prevented responsive to a second transition of the input data signal occurring before the delay time has elapsed.

Claims17

Dependent claims

A circuit comprising:

an input stage configured to receive an input data signal and further configured to receive a clock signal having a first phase and a second phase;
an output stage having a first driver circuit and a second driver circuit and configured to drive an output signal on an output node to a first state responsive to a first transition of the input data signal on an input node concurrent with the first phase of the clock signal, wherein the input stage is configured to activate a first driver circuit responsive to detecting the first transition of the input data signal and wherein the input stage is configured to cause the second driver circuit of the output stage to drive the output node to a second state responsive to the second transition irrespective of whether the second transition occurs before or after the delay time has elapsed;
a reverse stage having a first reverse circuit configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, and a second reverse circuit configured to assert a second inhibit signal at the delay time subsequent to activation of the second driver circuit, wherein the first driver circuit is configured to be deactivated responsive to assertion of the first inhibit signal and wherein the second driver circuit is configured to be deactivated responsive to assertion of the second inhibit signal, and wherein the reverse stage is further configured to prevent assertion of the first inhibit signal responsive to a second transition of the input data signal occurring before the delay time has elapsed subsequent to the first transition of the input data signal;
and
a feedback circuit having a respective input coupled to the output node and a respective output coupled to the first and second reverse circuits, wherein responsive to a state change of the output node, the feedback circuit is configured to drive a corresponding state change on its respective output at a delay time subsequent to the state change on the output node.

2 more elements

A repeater circuit comprising:

an input stage having first and second input circuits each coupled to receive an input data signal and a clock signal;
an output stage having first and second driver circuits each coupled to an output node, wherein the first driver circuit is configured to drive the output node responsive to activation of the first input circuit, and wherein the second driver circuit is configured to drive the output node responsive to activation of the second input circuit;
and
a reverse stage having first and second reverse circuits, wherein the first reverse circuit is configured to assert a first inhibit signal responsive to receiving a state signal in a first logic state and a feedback signal in the first logic state, and wherein the first reverse circuit is configured to cause the first driver circuit to be inactive responsive to assertion of the first inhibit signal;
and
wherein the second reverse circuit is configured to assert a second inhibit signal responsive to receiving the state signal in a second logic state and the feedback signal in the second logic state, wherein the second reverse circuit is configured to cause the second driver circuit to be inactive responsive to assertion of the second inhibit signal.

3 more elements

A circuit comprising:

a first input circuit coupled to receive an input data signal and a clock signal;
a second input circuit coupled to receive the input data signal and the clock signal;
a first driver circuit configured to drive an output signal on an output node to a logic high level, wherein the first input circuit is configured to activate the first driver circuit responsive to a low-to-high transition of the input data signal concurrent with the clock signal being high;
a second driver circuit configured to drive the output signal on the output node to a logic low level, wherein the second input circuit is configured to activate the second driver circuit responsive to a high-to-low transition of the input data signal concurrent with the clock signal being high;
a first reverse circuit configured to assert a first inhibit signal responsive to receiving a state signal at a logic high level and a feedback signal at the logic high level, and wherein the first reverse circuit is configured to cause the first driver circuit to be inactive responsive to assertion of the first inhibit signal;
and
a second reverse circuit configured to assert a second inhibit signal responsive to receiving the state signal in a logic low level and the feedback signal at the logic low level, wherein the second reverse circuit is configured to cause the second driver circuit to be inactive responsive to assertion of the second inhibit signal.

4 more elements

Dependencies are inferred from the claim text.