Family of multiplexer/flip-flops with enhanced testability

A multibit combined multiplexer and flip-flop circuit comprising:

• a plurality of bit circuits equal in number to a number of bits to the multibit combined multiplexer and flip-flop circuit, each bit circuit including
• a input section having
• an input terminal for each of a plurality of input signals,
• a plurality of input pass gates equal in number to the number of input terminals, each input pass gate having an input connected to a corresponding input terminal, an output and corresponding control terminals;
• a flip-flop section having an input connected to said output of each pass gate and an output;
• and
• a per bit control section having an inverter corresponding to each input terminal having an input and an output;
• a combined control section receiving a clock signal and at least one control signal indicating selection of only one of said input signals, said control section including a logical NAND for each input signal, said logical NAND having a first input receiving said clock signal and a second input receiving a corresponding input selection signal for a corresponding input signal and an output connected to a corresponding input of said inverters of said per bit control section;
• and
• wherein each input pass gate receives signals at said control terminals from a corresponding logical NAND and said corresponding inverter.