US 8,525,563 B2Granted

Semiconductor device including DLL circuit having coarse adjustment unit and fine adjustment unit

AssigneeElpida Memory, Inc.

InventorYutaka Uemura

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Abstract

Disclosed herein is a device that includes a coarse adjusting circuit generating first and second clock signals having different phases from each other, and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal. The fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal. The fine adjusting circuit controls the phase of the third clock signal by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes. The adjustment codes are not a binary system.

Claims20

Dependent claims

A semiconductor device comprising:

a coarse adjusting circuit generating first and second clock signals having different phases from each other;
and
a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal, wherein
the fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal,
the fine adjusting circuit controls the phase of the third clock signal in 2m+n steps by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes, where m is a natural number and n is a natural number equal to or smaller than 2m,
smallest one of the first transistors in size enables to change the phase of the third clock signal by one step, and largest one of the first transistors in size enables to change the phase of the third clock signal by smaller than 2m steps, and
smallest one of the second transistors in size enables to change the phase of the third clock signal by one step, and largest one of the second transistors in size enables to change the phase of the third clock signal by smaller than 2m steps.

4 more elements

A semiconductor device comprising:

a coarse adjusting circuit including a first input node, a first output node and a second output node, the first input node being configured to be supplied with a first clock signal, the first and second output nodes being configured to be respectively supplied with second and third clock signals of which phases are shifted from a phase of the first clock signal and different from each other;
and
a fine adjusting circuit including a third output node, a plurality of first delay circuits of which input nodes are coupled in common to the first output node of the coarse adjusting circuit and output nodes are coupled in common to the third output node, and a plurality of second delay circuits of which input nodes are coupled in common to the second output node of the coarse adjusting circuit and output nodes are coupled in common to the third output node, at least two of the first delay circuits being substantially equal in phase shift amount to each other, and at least two of the second delay circuits being substantially equal in phase shift amount to each other.

Dependencies are inferred from the claim text.