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US 8,525,557 B1Granted
Merged tristate multiplexer
AssigneeAltera Corporation
InventorDavid Lewis
Life of this patent
Estimating the term…
Abstract
Various methods and structures related to tristate multiplexer circuits are disclosed. An embodiment provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. This and other detailed embodiments are described more fully in the disclosure.
Claims19
A selection circuit comprising:
- a plurality of selectable input circuits, each including enable elements arranged such that any one of the plurality of selectable input circuits is operable to be enabled independently of other input circuits of the plurality of input circuits;
- an output circuit comprising first and second output transistors;
- and
- an output enable circuit coupled between the output circuit and the plurality of input circuits such that the output enable circuit is operable to provide a switching current pathway through an enabled input circuit for charging and discharging voltage at a gate of a transistor of the output circuit;
- wherein a selectable input circuit of the plurality of selectable input circuits comprises:
- a stacked PMOS transistor pair and a stacked NMOS transistor pair;
- wherein:
- a gate of a first transistor in the stacked PMOS transistor pair and a gate of a first transistor in the stacked NMOS transistor pair are directly connected for receiving an input signal;
- the enable elements comprise a second transistor in the stacked PMOS transistor pair and a second transistor in the stacked NMOS transistor pair;
- a drain of a transistor in the stacked PMOS transistor pair and a gate of one of the first and second output transistors are directly connected;
- and a drain of a transistor in the stacked NMOS transistor pair and a gate of another of the first and second output transistors are directly connected.
8 more elements
A selection circuit comprising:
- a plurality of selectable input circuits, each including enable elements arranged such that an input circuit of the plurality of input circuits is operable to be enabled independently of other input circuits of the plurality of input circuits;
- an output circuit including first and second output transistors;
- and
- an output enable circuit coupled between charging and discharging transistors of each of the plurality of input circuits, the output enable circuit operable to enable charging and discharging of an output circuit transistor gate voltage through a selected input circuit of the plurality of selectable input circuits;
- wherein a selectable input circuit of the plurality of selectable input circuits comprises:
- a stacked PMOS transistor pair and a stacked NMOS transistor pair;
- wherein:
- a gate of a first transistor in the stacked PMOS transistor pair and a gate of a first transistor in the stacked NMOS transistor pair are directly connected for receiving an input signal;
- the enable elements comprise a second transistor in the stacked PMOS transistor pair and a second transistor in the stacked NMOS transistor pair;
- a drain of a transistor in the stacked PMOS transistor pair and a gate of one of the first and second output transistors are directly connected;
- and a drain of a transistor in the stacked NMOS transistor pair and a gate of another of the first and second output transistors are directly connected.
8 more elements
Dependencies are inferred from the claim text.