Time-interleaved sample-and-hold
AssigneeCrest Semiconductors, Inc.
InventorsRamesh Kumar Singh, Yusuf Haque, Donald E. Lewis
Life of this patent
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Abstract
A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
Claims37
A time-interleaved sample-and-hold system, comprising:
- a first sample-and-hold circuit;
- and
- a second sample-and-hold circuit;
- wherein said first sample-and-hold circuit and said second sample-and-hold circuit share a common sampling switch;
- and
- timing adjustment circuitry for separately adjusting timing control signals to said sample-and-hold circuits based on timing of a timing control signal for said common sampling switch, wherein said timing adjustment circuitry dynamically adjusts the timing control signals to said sample-and-hold circuits during operation of said system using at least one timing trim control signal output from said timing adjustment circuitry.
A time-interleaved sample-and-hold system, comprising:
- a first sample-and-hold circuit comprising a first voltage storage element electrically coupled to a first switch and a second switch;
- a second sample-and-hold circuit comprising a second voltage storage element electrically coupled to a third switch and a fourth switch;
- an input node electrically coupleable to said first voltage storage element and said second voltage storage element through said first switch and said third switch, respectively;
- a common sampling switch electrically coupled to said second switch and said fourth switch;
- and
- timing adjustment circuitry for adjusting a timing control signal for at least one of said sample-and-hold circuits based on timing of a timing control signal for said common sampling switch, wherein said timing adjustment circuitry dynamically adjusts the timing control signals to said sample-and-hold circuits during operation of said system using at least one timing trim control signal output from said timing adjustment circuitry.
A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system, said method comprising dynamically adjusting a delay between a timing signal for a common sampling switch electrically coupled to said first and second sample-and-hold circuits and a timing signal for at least one of said sample-and-hold circuits to compensate for said timing offset using at least one timing trim control signal output from a timing adjustment circuitry.
Dependencies are inferred from the claim text.