Repeater circuit with multiplexer and state element functionality

An integrated circuit comprising:

• a first transmitter configured to drive a first signal on a first signal path;
• a second transmitter configured to drive a second signal on a second signal path;
• a clock generation circuit, wherein the clock generation circuit is configured to selectively enable one of a first clock signal associated with the first transmitter and a second clock signal associated with the second transmitter;
• and
• a repeater circuit including:
• a first input stage coupled to receive the first signal from the first signal path;
• a second input stage coupled to receive the second signal from the second signal path;
• an output stage configured to, when active, drive an output signal on an output node, wherein the first input stage is configured to activate the output stage responsive to a transition of the first clock signal, and wherein the second input stage is configured to activate the output stage responsive to a transition of the second clock signal;
• an intermediate stage coupled to the output stage, wherein the intermediate stage is configured to deactivate the output stage at a first delay time subsequent to one of the first or second input stages activating the output stage;
• and
• a storage element configured to store a state of the output signal, and further configured to cause the output node to be held at the state of the output signal subsequent to deactivation of the output stage.