Switching power supply and related control method

#1. Field of the Invention

#The present invention is related to a switching power supply, and more particularly, to a switching power supply which updates the limit signal of the present period according to the sampled value of the reference signal during the previous period.

#2. Description of the Prior Art

#FIG. 1 is a diagram illustrating a prior art switching power supply.

#FIG. 2 is a diagram illustrating a switching power supply according to the present invention.

#FIG. 3 is a diagram illustrating a sample/hold circuit according to the first embodiment of the present invention.

#Reference is made to FIG. 2 for a diagram illustrating a switching power supply 600 according to the embodiment of the present invention. Switching power supply 600, including a transformer 602, a power switch 604, an adjusting circuit 606, a detecting circuit 608, and a limit signal generator 610, can convert input voltage VIN into output voltage VOUT. Power switch 604 operates according to a switch control signal VSW: when power switch 604 is turned on, the current passing the primary coil of transformer 602 increases since transformer 602 is charged by input voltage VIN; when power switch 604 is turned off, the energy stored in the primary coil of transformer 602 is released by charging output capacitor Co through the secondary coil of transformer 602. Detecting circuit 608, including a resistor RCS coupled in series with power switch 604, can monitor the current passing power switch 604, thereby providing a corresponding detecting signal VCS. Limit signal generator 610, including a reference signal generator 618, a sample/hold circuit 700 and a clamping circuit 612, can provide a limit signal VLIMIT. Reference signal generator 618 provides a reference signal VREF(t) which varies with time t. Sample/hold circuit 700 samples reference signal VREF(t) according to the voltage level of switch control signal VSW and outputs the sampled reference signal as the new limit signal V′LIMIT for the next period. Clamping circuit 612 can maintain the maximum value of limit signal V′LIMIT at a predetermined value to avoid system overload. Therefore, if limit signal V′LIMIT does not exceed the predetermined value, limit signal VLIMIT outputted by clamping circuit 612 is equal to the limit signal V′LIMIT outputted by sample/hold circuit 700; if limit signal V′LIMIT exceeds the predetermined value, limit signal VLIMIT is kept at the predetermined value. Adjusting circuit 606 includes a comparator 614 and a driving circuit 616: comparator 614 includes a positive input end for receiving limit signal VLIMIT, a negative input end for receiving detecting signal VCS, and an output end for outputting a corresponding compare signal VCOMP according to the relationship between limit signal VLIMIT and detecting signal VCS; driving circuit 616 can generate the duty cycle of switch control signal VSW according to compare signal VCOMP, thereby controlling power switch 604.

#Reference is made to FIG. 3 for a diagram illustrating sample/hold circuit 700 according to the first embodiment of the present invention. Sample/hold circuit 700 includes two switches SW1 and SW2, two capacitors C1 and C2, and an inverter 70. With inverter 70, switches SW1 and SW2 can operate in a complimentary manner according to the voltage level of switch control signal VSW: when switch control signal VSW is at high level, switch SW1 is turned on (short circuit) and switch SW2 is turned off (open circuit); when switch control signal VSW is at low level, switch SW1 is turned off and switch SW2 is turned on.

#In the present embodiment, limit signal VLIMIT corresponding to each period has a specific value. For example, the values of limit signal VLIMIT corresponding to the periods T1-Tn are respectively represented by V1-Vn, while the time points when the detecting signal VCS reaches limit signal V1-Vn during periods T1-Tn are represented by t1-tn. Two continuous periods T1 and T2 are used for illustration. After entering period T1, switch control signal VSW maintains at high voltage level when detecting signal VCS does not exceed limit signal VLIMIT. Since switch SW1 is turned on and switch SW2 is turned off during this period, reference signal VREF(t) charges capacitor C1 so that the voltage level of reference signal VREF(t) is retained at memory terminal N1 of capacitor C1. After detecting signal VCS exceeds or is equal to limit signal VLIMIT at the time point t1, switch control signal VSW switches to low voltage level. Since switch SW1 is turned off and switch SW2 is turned on during this period, the charges stored in capacitor C1 is transmitted to capacitor C2. Based on charge distribution, the voltage level at memory terminal N2 of capacitor C2 can thus be updated to be the basis for determining the next limit signal V2 of the next period T2.