US 8,525,496 B2Granted

DC-DC converter and semiconductor chip

AssigneeKabushiki Kaisha Toshiba

InventorShouhei Kousai

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Abstract

A DC-DC converter including a first inductor connected between a second end of a first MOS transistor and an output terminal, a second inductor connected between a second end of a third MOS transistor and the output terminal, a first capacitor connected between the second MOS transistor and the third MOS transistor, a second capacitor connected between the fourth MOS transistor and the first MOS transistor and a third capacitor connected between the first MOS transistor and the third MOS transistor. Also included in the converter is a first resistor connected to a gate of the second MOS transistor, a second resistor connected to a gate of the fourth MOS transistor, and a first bias adjustment circuit which compares the output voltage with a preset first reference voltage and applies a first bias voltage to the resistors to make the output voltage equal to the first reference voltage.

Claims20

Dependent claims

A DC-DC converter comprising:

an output terminal which outputs an output voltage;
a first MOS transistor of a first conductivity type connected at a first end thereof to a first voltage line, a first voltage being applied to the first voltage line;
a second MOS transistor of a second conductivity type connected at a first end thereof to a second end of the first MOS transistor and connected at a second end thereof to a second voltage line, a second voltage being applied to the first voltage line and being different from the first voltage;
a third MOS transistor of the first conductivity type connected at a first end thereof to the first voltage line;
a fourth MOS transistor of the second conductivity type connected at a first end thereof to a second end of the third MOS transistor and connected at a second end thereof to the second voltage line;
a first inductor connected between the second end of the first MOS transistor and the output terminal;
a second inductor connected between the second end of the third MOS transistor and the output terminal;
a first capacitor connected between a gate of the second MOS transistor and the second end of the third MOS transistor;
a second capacitor connected between a gate of the fourth MOS transistor and the second end of the first MOS transistor;
a third capacitor connected at a first end thereof to the second end of the first MOS transistor and connected at a second end to the second end of the third MOS transistor;
a first resistor connected at a first end to the gate of the second MOS transistor;
a second resistor connected at a first end thereof to the gate of the fourth MOS transistor;
and
a first bias adjustment circuit which compares the output voltage with a preset first reference voltage and which applies a first bias voltage to a second end of the first resistor and a second end of the second resistor to make the output voltage equal to the first reference voltage.

11 more elements

A semiconductor chip comprising:

an LSI (Large Scale Integration) circuit;
and
a DC-DC converter which supplies an output voltage to the LSI circuit,
the DC-DC converter comprising:
an output terminal which outputs the output voltage;
a first MOS transistor of a first conductivity type connected at a first end thereof to a first voltage line, a first voltage being applied to the first voltage line;
a second MOS transistor of a second conductivity type connected at a first end thereof to a second end of the first MOS transistor and connected at a second end thereof to a second voltage line, a second voltage being applied to the first voltage line and being different from the first voltage;
a third MOS transistor of the first conductivity type connected at a first end thereof to the first voltage line;
a fourth MOS transistor of the second conductivity type connected at a first end thereof to a second end of the third MOS transistor and connected at a second end thereof to the second voltage line;
a first inductor connected between the second end of the first MOS transistor and the output terminal;
a second inductor connected between the second end of the third MOS transistor and the output terminal;
a first capacitor connected between a gate of the second MOS transistor and the second end of the third MOS transistor;
a second capacitor connected between a gate of the fourth MOS transistor and the second end of the first MOS transistor;
a third capacitor connected at a first end thereof to the second end of the first MOS transistor and connected at a second end to the second end of the third MOS transistor;
a first resistor connected at a first end to the gate of the second MOS transistor;
a second resistor connected at a first end thereof to the gate of the fourth MOS transistor;
and
a first bias adjustment circuit which compares the output voltage with a preset first reference voltage and which applies a first bias voltage to a second end of the first resistor and a second end of the second resistor to make the output voltage equal to the first reference voltage.

15 more elements

Dependencies are inferred from the claim text.