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US 8,525,356 B2Granted
Wiring substrate, manufacturing method thereof, and semiconductor package
AssigneeShinko Electric Industries Co., Ltd.
InventorsJunichi Nakamura, Kazuhiro Kobayashi
Life of this patent
Estimating the term…
Abstract
A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess.
Claims11
A wiring substrate comprising:
- a plurality of wiring layers;
- a plurality of insulating layers;
- an alignment mark embedded in an outermost insulating layer of the plurality of insulating layers, the outermost insulating layer being a surface of the wiring substrate;
- a pad embedded in the outermost insulating layer of the plurality of insulating layers;
- and
- a via forming a part of the wiring layers, the via being provided in the outermost insulating layer, the via being connected to a back surface of the pad,
- wherein a front face of the alignment mark is exposed on a surface of the outermost insulating layer,
- side and back faces of the alignment mark are coated by the outermost insulating layer,
- a front face of the pad is exposed on the surface of the outermost insulating layer,
- side and back faces of the pad are coated by the outermost insulating layer, and
- the front face of the alignment mark and the front face of the pad are roughened.
8 more elements
A wiring substrate comprising:
- a plurality of wiring layers;
- a plurality of insulating layers;
- an alignment mark embedded in an outermost insulating layer of the plurality of insulating layers, the outermost insulating layer being a surface of the wiring substrate;
- a pad embedded in the outermost insulating layer of the plurality of insulating layers;
- and
- a via forming a part of the wiring layers, the via being provided in the outermost insulating layer, the via being connected to a back surface of the pad,
- wherein a front face of the alignment mark is exposed on a surface of the outermost insulating layer,
- side and back faces of the alignment mark are coated by the outermost insulating layer,
- a front face of the pad is exposed on the surface of the outermost insulating layer,
- side and back faces of the pad are coated by the outermost insulating layer, and
- the front face of the alignment mark and the front face of the pad are roughened to have a surface roughness in a range greater than 50 nm and smaller than 200 nm.
8 more elements
A semiconductor package comprising:
- a semiconductor chip;
- and
- a wiring substrate, on which the semiconductor chip is mounted, the wiring substrate including
- a plurality of wiring layers,
- a plurality of insulating layers,
- an alignment mark embedded in an outermost insulating layer of the plurality of insulating layers, the outermost insulating layer being a surface of the wiring substrate,
- a pad embedded in the outermost insulating layer of the plurality of insulating layers, and
- a via forming a part of the wiring layers, the via being provided in the outermost insulating layer, the via being connected to a back surface of the pad,
- wherein a front face of the alignment mark is exposed on a surface of the outermost insulating layer,
- side and back faces of the alignment mark are coated by the outermost insulating layer,
- a front face of the pad is exposed on the surface of the outermost insulating layer,
- side and back faces of the pad are coated by the outermost insulating layer, and
- the front face of the alignment mark and the front face of the pad are roughened.
10 more elements
Dependencies are inferred from the claim text.