Chip package and method for forming the same

A method for forming a chip package, comprising:

• providing a substrate having an upper surface and a lower surface;
• forming a plurality of conducting pads located in the substrate or below the lower surface of the substrate, wherein an upper conducting pad of the conducting pads has at least an opening or a trench exposing a lower conducting pad of the conducting pads;
• forming a dielectric layer located between the conducting pads;
• forming a hole in the substrate, wherein the hole extends from the upper surface towards the lower surface, and the hole exposes a portion of the conducting pads;
• and
• forming a conducting layer in the hole, wherein the conducting layer is electrically connected to the conducting pads.

A chip package, comprising:

• a carrier substrate;
• a chip substrate having a front surface and a back surface, wherein the front surface of the chip substrate is bonded on the carrier substrate to form a bonding surface;
• a plurality of conducting pads located on the front surface of the chip substrate, wherein at least one conducting pad has a window, wherein the window is located in an upper conducting pad of the conducting pads, and wherein the window exposes a lower conducting pad of the conducting pads;
• a dielectric layer located between the conducting pads;
• a through-hole located in the carrier substrate and penetrating through the bonding surface and the window to expose one conducting pad or multiple conducting pads of the conducting pads;
• and
• a conducting layer located in the through hole and electrically connected to the one conducting pad or the multiple conducting pads.