Printed circuit board having different sub-core layers and semicondutor package comprising the same

A semiconductor package comprising:

• a printed circuit board (PCB);
• a semiconductor chip mounted on the PCB;
• and
• a molding portion having a coefficient of thermal expansion (CTE) and covering the semiconductor chip,
• wherein the PCB comprises:
• a core layer having a stacked structure including at least a first layer made of a first material and a second layer made of a second material different from the first material, wherein the second layer is disposed between the layer and the molding portion;
• an upper wiring layer disposed between the core layer and the semiconductor chip;
• and
• a lower wiring layer disposed on the core layer opposite to the upper wiring layer,
• wherein the first layer and second layer have different coefficients of thermal expansion CTEs, and
• wherein the CTE of the first layer has a value between the CTE of the molding portion and the CTE of the second layer.

A semiconductor package comprising:

• a printed circuit board (PCB);
• a semiconductor chip mounted on the PCB;
• and
• a molding portion covering the semiconductor chip,
• wherein the PCB comprises:
• a core layer having a vertically stacked structure including a upper layer made of a first material that has a first coefficient of thermal expansion (CTE) and a lower layer made of a second material that has a second CTE different from the first CTE;
• an upper wiring layer disposed on a first surface of the upper layer that comprises a top surface of the core layer, wherein a bottom surface of the upper wiring layer is adjacent the top surface of the core layer, and the upper wiring layer extends away from the top surface of the core layer, and wherein the upper wiring layer includes an upper circuit pattern and an upper insulation layer comprising an insulating material;
• and
• a lower wiring layer disposed on a first surface of the lower layer that comprises a bottom surface of the core layer opposite the top surface of the core layer, wherein a top surface of the lower wiring layer is adjacent the bottom surface of the core layer, and the lower wiring layer extends away from the bottom surface of the core layer, wherein the lower wiring layer includes a circuit pattern and a lower insulation layer comprising an insulating material,
• wherein each of the upper layer and the lower layer extend from a first end of the substrate to a second end of the substrate,
• wherein the molding portion has a third coefficient of thermal expansion (CTE), and
• wherein the second CTE of the lower layer has a value between the third CTE of the molding portion and the first CTE of the upper layer.